View RX62N_2313627.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

r01ds0052ej0110 rev.1.10 page 1 of 146 feb 10, 2011 datasheet RX62N/rx621 group renesas 32-bit mcu features 32-bit rx cpu core ? delivers 165 dmips at a maximum operating frequency of 100 mhz ? single precision 32-bit ieee-754 floating point ? accumulator: 32 32 to 64-bit result, one instruction ? mult/divide unit, 32 32 multiply in one cpu clock for multiple instructions ? interrupt response in as few as 5 cpu clock cycles ? cisc-harvard architecture with 5-stage pipeline ? variable length instruct ions, ultra compact code ? supports the memory protection unit (mpu) ? background jtag debug plus high-speed trace low power design and architecture ? 2.7v to 3.6v operation from a single supply ? 480 a/mhz run mode with all peripherals on ? deep software standby mode with rtc ? four low power modes main flash memory, no wait-state ? 100 mhz operation, 10 nsec read cycle ? no wait states for read at full cpu speed ? 256k, 384k, 512k byte size options ? for instructions or operands ? programming from usb, sci, jtag, user code data flash memory ? up to 32k bytes with 30k erase cycles ? background erase/program does not stall cpu sram, no wait-state ? 64k or 96k byte size options ? for operands or instructions ? back-up retention in deep software standby mode dma ? four fully programmable internal dma channels ? two exdma channels for external-to-external transfers ? data transfer controller (dtc) reset and supply management ? power-on reset (por) monitor/generator ? low voltage detect (lvd) with precision setting system clocking with clock monitoring ? external crystal, 8 mhz to 14 mhz to internal pll ? pll source to system, usb, and ethernet ? internal 125 khz loco for iwdt ? external crystal, 32 khz for rtc real time clock ? full calendar function, bcd format two independent watchdog timers ? 125-khz loco operation up to 14 communication interfaces ? (2) usb 2.0 full-speed interfaces with phy ? supports host/function/otg 10 endpoints for types: control, interrupt, bulk, isochronous ? (1) ethernet mac 10/100 mbps, half or full duplex supported. dedicated dma with 2-kbyte transmit and receive fifos. rmii or mii interface to external phy ? (1) can iso11898-1, supports 32 mailboxes ? (6) sci channels: asynchronous , clock sync, smartcard, and 9-bit modes ? (2) i 2 c interfaces up to 1m bps, smbus support ? (2) rspi external address space ? eight cs areas (8 16 mbytes) ? 128-mbyte sdram area ? 8-/16-/32-bit bus space selectable for each area tft-lcd up to wqvga resolution up to 20 extended function timers ? (12) 16-bit mtu2 input capture, output compare, pwm output, phase count mode ? (4) 8-bit tmr ? (4) 16-bit cmt 1-mhz adc units with tw o combinatio n choices ? 12-bit 8 ch. unit with single sample/hold circuit ? or (2) 10-bit 4 ch units eac h with a sample/hold circuit ? ad-converted value addition mode (12-bit a/d converter) 10-bit dac, 2 channels up to 128 gpio ? 5v tolerant, open-drain, internal pull-up operation temp ? ?40c to +85c tflga85 77mm, 0.65mm pitch tflga145 99mm, 0.65mm pitch lfbga176 1313mm, 0.8mm pitch lqfp100 1414mm, 0.5mm pitch lqfp144 2020mm, 0.5mm pitch 100 mhz 32-bit rx mcu with fpu, 165 dmips, up to 512-kbyte flash, ethernet, usb 2.0 full-speed host/function/ otg, can, 12-bit adc, tft-lcd, rtc, up to 14 communication channels features r01ds0052ej0110 rev.1.10 feb 10, 2011 www..net
r01ds0052ej0110 rev.1.10 page 2 of 146 feb 10, 2011 RX62N group, rx621 group 1. overview 1. overview 1.1 outline of specifications table 1.1 lists the specifications in outline, and table 1.2 lists the functions of products. table 1.1 outline of specifications (1 / 4) classification module/function description cpu cpu maximum operating frequency: 100 mhz 32-bit rx cpu minimum instruction execution time: one instru ction per state (cycle of the system clock) address space: 4-gbyte linear register set of the cpu general purpose: sixteen 32-bit registers control: nine 32-bit registers accumulator: one 64-bit register basic instructions: 73 floating-point instructions: 8 dsp instructions: 9 addressing modes: 10 data arrangement instructions: little endian data: selectable as little endian or big endian on-chip 32-bit multiplier: 32 x 32 ? 64 bits on-chip divider: 32 / 32 ? 32 bits barrel shifter: 32 bits memory-protection unit (mpu) (as an optional function) * 1 fpu single precision (32-bit) floating point data types and floating-point exceptions in conformance with the ieee754 standard memory rom rom capacity: 512 kbytes (max.) two on-board programming modes boot mode (the user mat is programmable via the sci and usb.) user program mode parallel programmer mode (for off-board programming) ram ram capacity: 96 kbytes (max.) data flash data flash capacity: 32 kbytes mcu operating modes single-chip mode, on-chip rom enabled expansion mode, and on-chip rom disabled expansion mode (software switching) clock clock generation circuit two circuits: main clock osci llator and subclock oscillator internal oscillator: low-speed on-chip oscillator structure of a pll frequency synthesizer and frequency divider for selectable operating frequency oscillation stoppage detection independent frequency-division and multiplicati on settings for the system clock (iclk), peripheral module clock (pclk), and external bus clock (bclk) the cpu and other bus masters run in synchronization with the system clock (iclk): 8 to 100 mhz peripheral modules run in synchroni zation with the peripheral module clock (pclk): 8 to 50 mhz devices connected to the external bus run in synchronization with the external bus clock (bclk): 8 to 50 mhz reset pin reset, power-on reset, voltage-monitoring reset, watchdog timer reset, independent watchdog timer reset, and deep software standby reset voltage detection circuit when the voltage on vcc falls below the voltage detection level (vdet), an internal reset or internal interrupt is generated. low power consumption low power consumption facilities module stop function four low power consumption modes sleep mode, all-module clock stop mode , software standby mode, and deep software standby mode
r01ds0052ej0110 rev.1.10 page 3 of 146 feb 10, 2011 RX62N group, rx621 group 1. overview interrupt interrupt control unit peripheral function interrupts: 146 sources external interrupts: 16 (pins irq0 to irq15) non-maskable interrupts: 3 (the nmi pin, osci llation stop detection interrupt, and voltage- monitoring interrupt) sixteen levels specifiable for the order of priority user break controller (as an optional function) two breakpoint channels address breaks in fetch cycles are specifiable (e nabling rom correction) external bus extension the external address space can be divided into nine areas (cs0 to cs7, sdcs), each with independent control of access settings. capacity of each area: 16 mbytes (cs0 to cs7), 128 mbytes (sdcs) a chip-select signal (cs0# to cs7#, sdcs#) can be output for each area. each area is specifiable as an 8-, 16-, or 32-bit bus space (however, only 176-pin versions support 32- bit bus spaces). the data arrangement in each area is selectabl e as little or big endian (only for data). sdram interface connectable bus format: separate buses wait control write buffer facility dma dma controller 4 channels three transfer modes: normal transfer, repeat transfer, and block transfer activation sources: software trigger, exter nal interrupts, and interrupt requests from peripheral functions exdma controller 2 channels four transfer modes: normal transfer, repeat transfer, block transfer, and cluster transfer single-address transfer enabled with the edack signal capable of direct data transfer to tft lcd panels activation sources: software trigger, ex ternal dma requests (edreq), and interrupt requests from peripheral functions data transfer controller three transfer modes: normal transfer, repeat transfer, and block transfer activation sources: software trigger, exte rnal interrupts and interrupt requests from peripheral functions i/o ports programmable i/o ports i/o ports for the 176-pin lfbga/145-pin tflga/144-pin lqfp/100-pin lqfp/85-pin tflga i/o pins: 126/103/103/72/58 input pins: 2/2/2/2/2 pull-up resistors: 56/44/44/40/28 open-drain outputs: 35/33/33/27/23 5-v tolerance: 11/11/11/7/6 timers multi-function timer pulse unit (16 bits x 6 channels) x 2 units time bases for the 12 16-bi t timer channels can be provided via up to 32 pulse-input/ output lines and six pulse-input lines select from among eight counter-input clo ck signals for each channel (pclk/1, pclk/4, pclk/16, pclk/64, mtclka, mtclkb, mtclkc, mtclkd) other than channel 5, for which only four signals are available. input capture function 21 output compare/input capture registers pulse output mode complementary pwm output mode reset synchronous pwm mode phase-counting mode generation of triggers for a/d converter conversion port output enable controls the high-impedance state of the mtu?s waveform output pins table 1.1 outline of specifications (2 / 4) classification module/function description
r01ds0052ej0110 rev.1.10 page 4 of 146 feb 10, 2011 RX62N group, rx621 group 1. overview timers programmable pulse generator (4 bits x 4 groups) x 2 units pulse output with the mtu output as a trigger maximum of 32-bit pulse output possible 8-bit timers (8 bits x 2 channels) x 2 units select from among seven internal clock signals (pclk, pclk/2, pclk/8, pclk/32, pclk/64, pclk/1024, pclk/8192) and one external clock signal capable of output of pulse trains with desired duty cycles or of pwm signals the 2 channels of each unit can be cascaded to create a 16-bit timer generation of triggers for a/d converter conversion capable of generating baud-rate clocks for sci5 and sci6 compare match timer (16 bits x 2 channels) x 2 units select from among four internal clock signals (pclk/8, pclk/32, pclk/128, pclk/512) watchdog timer 8 bits x 1 channel select from among eight counter-input clo ck signals (pclk/4, pclk/64, pclk/128, pclk/512, pclk/2048, pclk/8192, pclk/32768, pclk/131072) switchable between watchdog timer mode and interval timer mode independent watchdog timer 14 bits x 1 channel counter-input clock: dedicated on-chip oscillator realtime clock clock source: subclock time/calendar interrupt sources: alarm interrupt, periodic interrupt, and carry interrupt communication function ethernet controller input and output of ethernet/ieee 802.3 frames transfer at 10 or 100 mbps full- and half-duplex modes mii (media independent interface) or rmii (reduced media independent interface) as defined in ieee 802.3u detection of magic packets tm * or output of a "wake-on-lan" signal (wol) compliance with flow control as defined in ieee 802.3x standards note: * magic packet tm is a registered trademark of advanced micro devices, inc. dma controller for ethernet controller alleviation of cpu loads by the descriptor control method transmission fifo: 2 kbytes; reception fifo: 2 kbytes usb 2.0 host/ function module includes a udc (usb device controller) and transceiver for usb 2.0 single port (176-pin products: two ports) compliance with the usb 2.0 specification transfer rate: full speed (12 mbps) self-power mode and bus power are selectable otg (on the go) operation is possible incorporates 2 kbytes of ram as a transfer buffer serial communications interfaces 6 channels serial communications modes: asynchronous, clock synchronous, and smart-card interface multi-processor communications function on-chip baud rate generator allows selection of the desired bit rate choice of lsb-first or msb-first transfer average transfer rate clock can be input from tmr timers for sci5 and sci6 table 1.1 outline of specifications (3 / 4) classification module/function description
r01ds0052ej0110 rev.1.10 page 5 of 146 feb 10, 2011 RX62N group, rx621 group 1. overview note 1. as for the mpu, contact your renesas sales agency. note 2. for products in the 100-pin lqfp and 85-pi n tflga, bclk is synchronized with 8 to 25 mhz. note 3. msb-first order is only avail able in the smart-card interface mode. communication function i 2 c bus interfaces 2 channels (100-pin version: 1 channel) communications formats i 2 c bus format/smbus format master/slave selectable (for multi-master operation) can module 1 channel 32 mailboxes serial peripheral interfaces 2 channels rspi transfer facility using the mosi (master out, slave in), miso (master in, slave out), ssl (slave select), and rspi clock (rspck) signals enables serial transfer through spi operation (four lines) or clock-synchronous operation (three lines) capable of handling serial transfer as a master or slave data formats switching between msb first and lsb first the number of bits in each transfer can be changed to any number of bits from 8 to 16, or to 20, 24, or 32 bits. 128-bit buffers for transmission and reception up to four frames can be transmitted or re ceived in a single transfer operation (with each frame having up to 32 bits) buffered structure double buffers for both transmission and reception 12-bit a/d converter 10-bit a/d converter 12 bits x 1 unit (1 unit x 8 channels) or 10 bits x 2 units (2 units x 4 channels); 12- and 10-bit a/d converters can be exclusively used. 10- or 12-bit resolution conversion time: 1.0 ? s per channel (in operation with pclk at 50 mhz) two operating modes single mode scan mode (one-cycle scan m ode or continuous scan mode) sample-and-hold function three ways to start a/d conversion conversion can be started by software, a conv ersion start trigger from a timer (mtu or tmr), or an external trigger signal. self-diagnostic functions d/a converter 2 channels (1 channel for 100-pin products) 10-bit resolution output voltage: 0 v to vrefh crc calculator crc code generation for arbitrary amounts of data in 8-bit units select any of three generating polynomials: x 8 + x 2 + x + 1, x 16 + x 15 + x 2 + 1, or x 16 + x 12 + x 5 + 1. generation of crc codes for use with l sb-first or msb-first communications is selectable. operating frequency 8 to 100 mhz power supply voltage vcc = pllvcc = avcc = 2.7 to 3.6v, vrefh = 2.7 to avcc operating temperature ?40 to +85 ? c package 176-pin lfbga (plbg0176ga- a), 145-pin tflga (ptlg0145jb-a), 144-pin lqfp (plqp0144ka-a), 100-pin lqfp (plqp0100kb-a) * 2 85-pin tflga (ptlg0085ja-a) * 2, * 3 table 1.1 outline of specifications (4 / 4) classification module/function description
r01ds0052ej0110 rev.1.10 page 6 of 146 feb 10, 2011 RX62N group, rx621 group 1. overview [legend] o: supported, ? : not supported note: * for details on part numbers, see table 1.3. table 1.2 functions of RX62N group and rx621 group products functions RX62N group rx621 group r5f562nxbxxx * r5f562nxaxxx * r5f5621xbxxx * package 176-pin lfbga 145-pin tflga 144-pin lqfp 100-pin lqfp 176-pin lfbga 145-pin tflga 144-pin lqfp 100-pin lqfp 176-pin lfbga 145-pin tflga 144-pin lqfp 100-pin lqfp 85-pin tflga external bus sdram area controller o ? o ? o ? dma dma controller o o o exdma controller o ? o ? o ? data transfer controller o o o timers multi-function timer pulse unit o o o port output enable o o o ? programmable pulse generator o o o 8-bit timers o o o compare match timer o o o realtime clock o o o watchdog timer o o o independent watchdog timer o o o communication function ethernet controller/ dma controller for ethernet controller oo ? usb 2.0 host/function module o o o serial communications interfaces o o o i 2 c bus interfaces o o o can module o ? o serial peripheral interfaces o o o a/d converter o o o d/a converter o o o crc calculator o o o
r01ds0052ej0110 rev.1.10 page 7 of 146 feb 10, 2011 RX62N group, rx621 group 1. overview 1.2 list of products table 1.3 is a list of products, and figure 1.1 shows how to read the product part no. table 1.3 list of products group part no. package rom capacity ram capacity data flash operating frequency (max.) RX62N r5f562n8bdbg plbg0176ga-a 512 kbytes 96 kbytes 32 kbytes 100 mhz r5f562n8bdle ptlg0145jb-a 512 kbytes 96 kbytes 32 kbytes 100 mhz r5f562n8bdfb plqp0144ka-a 512 kbytes 96 kbytes 32 kbytes 100 mhz r5f562n8bdfp plqp0100kb-a 512 kbytes 96 kbytes 32 kbytes 100 mhz r5f562n7bdbg plbg0176ga-a 384 kbytes 64 kbytes 32 kbytes 100 mhz r5f562n7bdle ptlg0145jb-a 384 kbytes 64 kbytes 32 kbytes 100 mhz r5f562n7bdfb plqp0144ka-a 384 kbytes 64 kbytes 32 kbytes 100 mhz r5f562n7bdfp plqp0100kb-a 384 kbytes 64 kbytes 32 kbytes 100 mhz r5f562n8adbg plbg0176ga-a 512 kbytes 96 kbytes 32 kbytes 100 mhz r5f562n8adle ptlg0145jb-a 512 kbytes 96 kbytes 32 kbytes 100 mhz r5f562n8adfb plqp0144ka-a 512 kbytes 96 kbytes 32 kbytes 100 mhz r5f562n8adfp plqp0100kb-a 512 kbytes 96 kbytes 32 kbytes 100 mhz r5f562n7adbg plbg0176ga-a 384 kbytes 64 kbytes 32 kbytes 100 mhz r5f562n7adle ptlg0145jb-a 384 kbytes 64 kbytes 32 kbytes 100 mhz r5f562n7adfb plqp0144ka-a 384 kbytes 64 kbytes 32 kbytes 100 mhz r5f562n7adfp plqp0100kb-a 384 kbytes 64 kbytes 32 kbytes 100 mhz rx621 r5f56218bdbg plbg0176ga-a 512 kbytes 96 kbytes 32 kbytes 100 mhz r5f56218bdle ptlg0145jb-a 512 kbytes 96 kbytes 32 kbytes 100 mhz r5f56218bdfb plqp0144ka-a 512 kbytes 96 kbytes 32 kbytes 100 mhz r5f56218bdfp plqp0100kb-a 512 kbytes 96 kbytes 32 kbytes 100 mhz r5f56218bdld ptlg0085ja-a 512 kbytes 96 kbytes 32 kbytes 100 mhz r5f56217bdbg plbg0176ga-a 384 kbytes 64 kbytes 32 kbytes 100 mhz r5f56217bdle ptlg0145jb-a 384 kbytes 64 kbytes 32 kbytes 100 mhz r5f56217bdfb plqp0144ka-a 384 kbytes 64 kbytes 32 kbytes 100 mhz r5f56217bdfp plqp0100kb-a 384 kbytes 64 kbytes 32 kbytes 100 mhz r5f56217bdld ptlg0085ja-a 384 kbytes 64 kbytes 32 kbytes 100 mhz r5f56216bdbg plbg0176ga-a 256 kbytes 64 kbytes 32 kbytes 100 mhz r5f56216bdle ptlg0145jb-a 256 kbytes 64 kbytes 32 kbytes 100 mhz r5f56216bdfb plqp0144ka-a 256 kbytes 64 kbytes 32 kbytes 100 mhz r5f56216bdfp plqp0100kb-a 256 kbytes 64 kbytes 32 kbytes 100 mhz r5f56216bdld ptlg0085ja-a 256 kbytes 64 kbytes 32 kbytes 100 mhz
r01ds0052ej0110 rev.1.10 page 8 of 146 feb 10, 2011 RX62N group, rx621 group 1. overview figure 1.1 how to read the product part no. indicates the type of memory. f: flash memory version r5 indicates the package type, number of pins, and pin pitch . bg: lfbga176-0.80 le: tflga145-0.65 fb: lqfp144-0.50 fp: lqfp100-0.50 ld: tflga85-0.65 indicates the rom capacity, ram capacity, and data flash capacity. 8: 512 kbytes/96 kbytes/32 kbytes 7: 384 kbytes/64 kbytes/32 kbytes 6: 256 kbytes/64 kbytes/32 kbytes indicates a renesas mcu. indicates a renesas semiconductor product. a: the can module is not included. b: can 1 channel indicates a group name 2n: RX62N group 21: rx621 group indicates the rx600 series. f5 6 2 n 7bdb g
r01ds0052ej0110 rev.1.10 page 9 of 146 feb 10, 2011 RX62N group, rx621 group 1. overview 1.3 block diagram figure 1.2 shows a block diagram. figure 1.2 block diagram instruction bus external bus port 0 port 1 port 2 port 4 port 5 port 6 port 7 port 8 port 9 port a port b port c port d port e clock generation circuit 10-bit a/d converter 4 channels (unit 1) 10-bit a/d converter 4 channels (unit 0) 12-bit a/d converter 8 channels tmr 2 channels (unit 1) tmr 2 channels (unit 0) mtu 6 channels (unit 1) mtu 6 channels (unit 0) ppg (unit 1) ppg (unit 0) 10-bit d/a converter 2 channels cmt 2 channels (unit 1) sci 6ch wdt riic 2 channels data flash crc cmt 2 channels (unit 0) port f port g iwdt usb (up to 2 ports) rspi (unit 1) can rtc rspi (unit 0) poe notes: 1. the installation of the exdmac, etherc, edmac, usb, can module, poe, and ports 0 to g is different depending on the product group and package. 2. for detail on the bus configuration of internal peripheral buses, see section 12, buses. 3. the number of riic units and 10-bit d/a converter channels that are inco rporated differs with the package. * 1 * 1 * 1 port 3 * 1 operand bus internal main bus 2 etherc edmac icu dtc dmaca * 1 * 1 exdmac * 1 internal peripheral bus 1 to 6 bsc internal main bus 1 * 2 etherc: ethernet controller edmac: dma controller for ethernet controller icu: interrupt control unit dtc: data transfer controller dmaca: dma controller exdmac: exdma controller bsc: bus controller wdt: watchdog timer iwdt: independent watchdog timer crc: crc (cyclic redundancy check) calculator mpu: memory-protection unit sci: serial communications interfaces usb: usb 2.0 host/function module rspi: serial peripheral interfaces can: can module mtu: multi-function timer pulse unit poe: port output enable ppg: programmable pulse generator tmr: 8-bit timer cmt: compare match timer rtc: realtime clock riic: i 2 c bus interface rx cpu mpu ram rom * 3 * 3
r01ds0052ej0110 rev.1.10 page 10 of 146 feb 10, 2011 RX62N group, rx62 1 group 1. overview 1.4 pin assignments figure 1.3 to figure 1.9 show the pins assignments. table 1.4 to table 1.8 show the list of pins and pin functions. figure 1.3 pin assignment of the 176-pin lfbga p70 pe2 p64 p62 p60 pd6 p97 p96 pd1 p91 p47 p44 vrefl vrefh p02 pe6 pe5 pe3 pe0 vcc pd5 vcc p94 p92 vcc p40 p07 p05 p03 p00 p65 pe7 pe4 vss p41 vcc p01 emle p67 p66 vcc vss bscanp cnvss xcin pg5 pa0 pg3 vss vcl wdtovf# xcout pa1 pg6 vcc mde md0 md1 vss pa3 pa4 pa2 res# vcc p35 xtal pa6 pa7 pa5 p34 pf3 p32 extal pb0 p72 p71 pf4 pf0 p31 p33 vcc pb3 pb4 p30 vcc p27 pf2 pb2 pb6 vcc pc0 p81 pc6 vss p51 p54 p55 p11 vss p22 p25 pf1 pb5 p73 p74 pc2 pc3 pc5 vcc p52 p10 p57 p15 p17 p20 p23 p26 pb7 pc1 p76 pc4 p82 p50 p84 vcc_ usb p56 vcc_ usb p13 p14 p16 pllvcc p24 pe1 p63 p61 pd7 pg0 pd4 pd3 pd2 pd0 p90 p46 p45 p42 avcc avss p75 p77 p80 pc7 p83 p53 p85 usb1_ dp usb1_ dm vss_ usb usb0_ dp usb0_ dm p12 pllvss p21 bcdefghj klmnp a r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 bcdefghj klmnp a r RX62N group rx621 group plbg0176ga-a (176-pin lfbga) (upper perspective view) : nc pin vss pb1 vss pg7 vss pg4 pg2 vss pg1 vss p95 p93 p43 vss
r01ds0052ej0110 rev.1.10 page 11 of 146 feb 10, 2011 RX62N group, rx62 1 group 1. overview figure 1.4 pin assignment of the 145-pin tflga nc RX62N group rx621 group ptlg0145jb-a (145-pin tflga) (upper perspective view) : nc pin v c l v s s p 0 0 b s c a n p p 6 5 p 6 7 p a 0 p 6 6 x c i n x c o u t w d t o v f # m d e p a 1 p a 3 v c c p a 2 x t a l v s s m d 1 m d 0 v s s p a 5 p a 6 p a 4 e x t a l p 3 4 v c c r e s # p b 0 p 7 1 p b 1 p a 7 p 3 3 p 2 7 p 3 5 p 3 2 p b 2 p b 4 p b 5 p 7 2 p 3 0 p 2 4 p 3 1 p 2 6 p 5 3 v s s p c 7 p 8 2 p c 3 p b 7 p 7 3 p c 0 p b 3 p 2 5 p 2 2 p 1 7 p 1 2 v c c _ u s b p 5 6 p 5 2 p 8 3 p 8 1 p 7 7 p 7 5 v c c p b 6 p 2 3 p 2 0 p l l v c c p 1 5 p 1 4 v s s _ u s b p 5 5 p 5 0 p c 6 p 8 0 p c 2 p c 1 v s s p 2 1 p 1 6 p l l v s s p 1 3 u s b 0 _ d m u s b 0 _ d p p 5 4 p 5 1 v c c p c 5 p c 4 p 7 6 p 7 4 13 12 11 10 9 8 7 6 5 4 3 2 1 bcdefghj klmn a bcdefghj klmn a 13 12 11 10 9 8 7 6 5 4 3 2 1 p 0 1 p 0 5 v s s p 4 1 p 4 6 p 9 2 p d 2 p d 7 p 6 1 p 6 3 p e 5 p e 3 p 7 0 p 0 3 p 0 7 v r e f h p 4 0 p 4 5 p 9 0 p d 1 p d 5 v s s p e 0 p e 2 p e 1 p e 4 a v s s a v c c v r e f l p 4 2 p 4 4 p 4 7 p 9 1 p d 0 p d 6 p 6 0 p 6 2 p 6 4 p d 3 e m l e v c c p 0 2 p 4 3 v c c v s s p 9 3 p d 4 v c c v s s v c c p e 7 p e 6
r01ds0052ej0110 rev.1.10 page 12 of 146 feb 10, 2011 RX62N group, rx62 1 group 1. overview figure 1.5 pin assignment of the 144-pin lqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 pe0/d8/sslb1-b p64/cs4#-a/we# p63/cs3#-a/cas# p62/cs2#-a/ras# p61/cs1#-a/sdcs# vss p60/cs0#-a vcc pd7/d7/mtic5u/poe0# pd6/d6/mtic5v/poe1# pd5/d5/mtic5w/poe2# pd4/d4/mtic11u-b/poe3# pd2/d2/mtic11w-b/poe5# pd1/d1/poe6# pd0/d0/poe7# p93/a19-b p92/a18-b p91/a17-b vss p90/a16-b vcc p47/an7/irq15-b p46/an6/irq14 p45/an5/irq13-b p44/an4/irq12 p43/an3/irq11-b p42/an2/irq10-b p41/an1/irq9-b vrefl p40/an0/irq8-b vrefh p07/adtrg0#-a/irq15-a pe1/d9/sslb2-b pd3/d3/mtic11v-b/poe4# avcc p74/cs4#-b/et_erxd1/rmii_rxd1 pc2/a18-a/mtclke-a/rxd5/ssla3-a/et_rx_dv p76/cs6#-b/et_rx_clk/ref50ck p77/cs7#-b/et_rx_er/rmii_rx_er pc3/a19-a/mtclkf-a/txd5/et_tx_er pc4/a20/cs3#-c/mtclkc-b/ssla0-a/et_tx_clk p80/edreq0-a/mtioc3b-b/et_tx_en/rmii_txd_en/trdata0 p81/edack0-a/mtioc3d-b/et_etxd0/rmii_txd0/trdata1 p82/edreq1-a/mtioc4a-b/et_etxd1/rmii_txd1/trsync pc5/a21/cs2#-c/wait#-c/mtic11w-a/mtclkd-b/rspcka-a/et_etxd2 pc6/a22/cs1#-c/mtic11v-a/mtclka-b/mosia-a/et_etxd3 pc7/a23/cs0#-b/mtic11u-a/mtclkb-b/misoa-a/et_col vcc vss p50/wr0#/wr#/txd2-b/sslb1-a p51/wr1#/bc1#/wait#-d/sck2/sslb2-a p52/rd#/rxd2-b/sslb3-a p53/bclk p54/edack0-c/mtioc4b-b/et_linksta/trdata2 p55/wait#-b/edreq0-c/mtioc4d-b/et_exout/trdata3 p56/edack1-c/mtioc3c-b vss_usb usb0_dp usb0_dm vcc_usb p12/tmci1-b/rxd2-a/scl0/irq2-b p13/adtrg1#/tmo3/txd2-a/sda0/irq3-b p14/tmri2/irq4-b/usb0_ovrcura/usb0_dpupe-b p15/po13/mtioc0b/tmci2-a/sck3-a/irq5-b pllvss p16/po14/mtioc3c-a/tmo2/rxd3-a/irq6-b/usb0_vbus/usb0_ovrcurb/usb0_vbusen-b pllvcc p20/po0/mtioc1a/tmri0-b/txd0/sda1/usb0_id p75/cs5#-b/et_erxd0/rmii_rxd0 p83/edack1-a/mtioc4c-b/et_crs/rmii_crs_dv/trclk p17/po15/mtioc3a/txd3-a/irq7-b pe3/d11/poe8# pe5/d13/rspckb-b/irq5-a vss p70/sdclk vcc pe6/d14/mosib-b/irq6-a pe7/d15/misob-b/irq7-a p65/cs5#-a/cke p66/cs6#-a/dqm0 p67/cs7#-a/dqm1 pa0/a0/bc0#/po16/mtioc6a/ssla1-b pa1/a1/po17/mtioc6b/ssla2-b pa2/a2/po18/mtioc6c/ssla3-b vss pa4/a4/po20/mtioc7a/ssla0-b vcc pa5/a5/po21/mtioc7b/rspcka-b pa6/a6/po22/mtioc8a/mosia-b pa7/a7/po23/mtioc8b/misoa-b pb0/a8/po24/mtioc9a p71/cs1#-b/et_mdio p72/cs2#-b/et_mdc pb1/a9/po25/mtioc9c pb2/a10/po26/mtioc9b/mtclkg-b pb3/a11/po27/mtioc9d/mtclkh-b pb4/a12/po28/mtioc10a/mtclke-b pb5/a13/po29/mtioc10c/mtclkf-b pb6/a14/po30/mtioc10b pb7/a15/po31/mtioc10d p73/cs3#-b/et_wol vss pc0/a16-a/mtclkg-a/ssla1-a/et_erxd3 pc1/a17-a/mtclkh-a/sck5/ssla2-a/et_erxd2 pe4/d12/sslb0-b pa3/a3/po19/mtioc6d vcc avss vcc p03/da0/irq11-a vss p02/tmci1-a/sck6-a/irq10-a p01/tmci0-a/rxd6-a/irq9-a p00/tmri0-a/txd6-a/irq8-a bscanp emle wdtovf# vss mde vcl md0 xcin xcout res# xtal vss extal vcc p35/nmi p34/po12/mtioc0a/tmci3/sck6-b/irq4-a/trst# p32/po10/mtioc0c/txd6-b/ctx0/irq2-a/rtcout p31/po9/mtioc4d-a/tmci2-b/sslb0-a/irq1/tms p30/po8/mtioc4b-a/tmri3/rxd1/misob-a/irq0/tdi p27/cs7#-c/po7/mtioc2b/sck1/rspckb-a/tck p26/cs6#-c/po6/mtioc2a/tmo1/txd1/mosib-a/tdo p25/cs5#-c/edack1-b/adtrg0#-b/po5/mtioc4c-a/mtclkb-a/rxd3-b/usb0_dprpd p24/cs4#-c/edreq1-b/po4/mtioc4a-a/mtclka-a/tmri1/sck3-b/usb0_vbusen-a p23/edack0-b/po3/mtioc3d-a/mtclkd-a/txd3-b/usb0_dpupe-a p21/po1/mtioc1b/tmci0-b/rxd0/scl1/usb0_exicen p05/da1/irq13-a md1 p22/edreq0-b/po2/mtioc3b-a/mtclkc-a/tmo0/sck0/usb0_drpd p33/po11/mtioc0d/rxd6-b/crx0/irq3-a pe2/d10/sslb3-b/poe9# RX62N group rx621 group plqp0144ka-a (144-pin lqfp) (top view)
r01ds0052ej0110 rev.1.10 page 13 of 146 feb 10, 2011 RX62N group, rx62 1 group 1. overview figure 1.6 pin assignment of th e 144-pin lqfp (a ssistance diagram) p74/cs4#-b/et_erxd1/rmii_rxd1 pc2/a18-a/mtclke-a/rxd5/ssla3-a/et_rx_dv p76/cs6#-b/et_rx_clk/ref50ck p77/cs7#-b/et_rx_er/rmii_rx_er pc3/a19-a/mtclkf-a/txd5/et_tx_er pc4/a20/cs3#-c/mtclkc-b/ssla0-a/et_tx_clk p80/edreq0-a/mtioc3b-b/et_tx_en/rmii_txd_en/trdata0 p81/edack0-a/mtioc3d-b/et_etxd0/rmii_txd0/trdata1 p82/edreq1-a/mtioc4a-b/et_etxd1/rmii_txd1/trsync pc5/a21/cs2#-c/wait#-c/mtic11w-a/mtclkd-b/rspcka-a/et_etxd2 pc6/a22/cs1#-c/mtic11v-a/mtclka-b/mosia-a/et_etxd3 pc7/a23/cs0#-b/mtic11u-a/mtclkb-b/misoa-a/et_col vcc vss p50/wr0#/wr#/txd2-b/sslb1-a p51/wr1#/bc1#/wait#-d/sck2/sslb2-a p52/rd#/rxd2-b/sslb3-a p53/bclk p54/edack0-c/mtioc4b-b/et_linksta/trdata2 p55/wait#-b/edreq0-c/mtioc4d-b/et_exout/trdata3 p56/edack1-c/mtioc3c-b vss_usb usb0_dp usb0_dm vcc_usb p12/tmci1-b/rxd2-a/scl0/irq2-b p13/adtrg1#/tmo3/txd2-a/sda0/irq3-b p14/tmri2/irq4-b/usb0_ovrcura/usb0_dpupe-b p15/po13/mtioc0b/tmci2-a/sck3-a/irq5-b pllvss p16/po14/mtioc3c-a/tmo2/rxd3-a/irq6-b/usb0_vbus/usb0_ovrcurb/usb0_vbusen-b pllvcc p20/po0/mtioc1a/tmri0-b/txd0/sda1/usb0_id p75/cs5#-b/et_erxd0/rmii_rxd0 p83/edack1-a/mtioc4c-b/et_crs/rmii_crs_dv/trclk p17/po15/mtioc3a/txd3-a/irq7-b pe3/d11/poe8# pe5/d13/rspckb-b/irq5-a vss p70/sdclk vcc pe6/d14/mosib-b/irq6-a pe7/d15/misob-b/irq7-a p65/cs5#-a/cke p66/cs6#-a/dqm0 p67/cs7#-a/dqm1 pa0/a0/bc0#/po16/mtioc6a/ssla1-b pa1/a1/po17/mtioc6b/ssla2-b pa2/a2/po18/mtioc6c/ssla3-b vss pa4/a4/po20/mtioc7a/ssla0-b vcc pa5/a5/po21/mtioc7b/rspcka-b pa6/a6/po22/mtioc8a/mosia-b pa7/a7/po23/mtioc8b/misoa-b pb0/a8/po24/mtioc9a p71/cs1#-b/et_mdio p72/cs2#-b/et_mdc pb1/a9/po25/mtioc9c pb2/a10/po26/mtioc9b/mtclkg-b pb3/a11/po27/mtioc9d/mtclkh-b pb4/a12/po28/mtioc10a/mtclke-b pb5/a13/po29/mtioc10c/mtclkf-b pb6/a14/po30/mtioc10b pb7/a15/po31/mtioc10d p73/cs3#-b/et_wol vss pc0/a16-a/mtclkg-a/ssla1-a/et_erxd3 pc1/a17-a/mtclkh-a/sck5/ssla2-a/et_erxd2 pe4/d12/sslb0-b pa3/a3/po19/mtioc6d vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 pe0/d8/sslb1-b p64/cs4#-a/we# p63/cs3#-a/cas# p62/cs2#-a/ras# p61/cs1#-a/sdcs# vss p60/cs0#-a vcc pd7/d7/mtic5u/poe0# pd6/d6/mtic5v/poe1# pd5/d5/mtic5w/poe2# pd4/d4/mtic11u-b/poe3# pd2/d2/mtic11w-b/poe5# pd1/d1/poe6# pd0/d0/poe7# p93/a19-b p92/a18-b p91/a17-b vss p90/a16-b vcc p47/an7/irq15-b p46/an6/irq14 p45/an5/irq13-b p44/an4/irq12 p43/an3/irq11-b p42/an2/irq10-b p41/an1/irq9-b vrefl p40/an0/irq8-b vrefh p07/adtrg0#-a/irq15-a pe1/d9/sslb2-b pd3/d3/mtic11v-b/poe4# avcc avss vcc p03/da0/irq11-a vss p02/tmci1-a/sck6-a/irq10-a p01/tmci0-a/rxd6-a/irq9-a p00/tmri0-a/txd6-a/irq8-a bscanp emle wdtovf# vss mde vcl md0 res# xtal vss extal vcc p34/po12/mtioc0a/tmci3/sck6-b/irq4-a/trst# p31/po9/mtioc4d-a/tmci2-b/sslb0-a/irq1/tms p30/po8/mtioc4b-a/tmri3/rxd1/misob-a/irq0/tdi p27/cs7#-c/po7/mtioc2b/sck1/rspckb-a/tck p26/cs6#-c/po6/mtioc2a/tmo1/txd1/mosib-a/tdo p25/cs5#-c/edack1-b/adtrg0#-b/po5/mtioc4c-a/mtclkb-a/rxd3-b/usb0_dprpd p24/cs4#-c/edreq1-b/po4/mtioc4a-a/mtclka-a/tmri1/sck3-b/usb0_vbusen-a p23/edack0-b/po3/mtioc3d-a/mtclkd-a/txd3-b/usb0_dpupe-a p21/po1/mtioc1b/tmci0-b/rxd0/scl1/usb0_exicen p05/da1/irq13-a md1 p22/edreq0-b/po2/mtioc3b-a/mtclkc-a/tmo0/sck0/usb0_drpd pe2/d10/sslb3-b/poe9# p35/nmi p33/po11/mtioc0d/rxd6-b/crx0/irq3-a p32/po10/mtioc0c/txd6-b/ctx0/irq2-a/rtcout 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 RX62N group rx621 group plqp0144ka-a (144-pin lqfp) (top view) 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 xcin xcout
r01ds0052ej0110 rev.1.10 page 14 of 146 feb 10, 2011 RX62N group, rx62 1 group 1. overview figure 1.7 pin assignment of the 100-pin lqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 pe0/d8/sslb1-b pd7/d7/mtic5u/poe0# pd6/d6/mtic5v/poe1# pd5/d5/mtic5w/poe2# pd4/d4/mtic11u-b/poe3# pd3/d3/mtic11v-b/poe4# pd2/d2/mtic11w-b/poe5# pd1/d1/poe6# pd0/d0/poe7# p47/an7/irq15-b p46/an6/irq14 p45/an5/irq13-b p43/an3/irq11 p42/an2/irq10 p41/an1/irq9 vrefl p40/an0/irq8 vrefh avcc p07/adtrg0#-a/irq15-a avss pe1/d9/sslb2-b p44/an4/irq12 pc2/a18/mtclke-a/rxd5/ssla3-a/et_rx_dv pc4/a20/cs3#/mtclkc-b/ssla0-a/et_tx_clk pc5/a21/cs2#/wait#-c/mtic11w-a /mtclkd-b/rspcka-a/et_etxd2 pc6/a22/cs1#/mtic11v-a/mtclka-b/mosia-a/et_etxd3 pc7/a23/cs0#/mtic11u-a/mtclkb-b/misoa-a/et_col p50/wr0#/wr#/txd2-b/sslb1-a p51/wr1#/bc1#/wait#-d/sck2/sslb2-a p52/rd#/rxd2-b/sslb3-a p53/bclk p54/mtioc4b-b p55/wait#-b/mtioc4d-b vss_usb usb0_dp vcc_usb p12/tmci1/rxd2-a/scl0/irq2-b p13/adtrg1#/po13/mtioc0b/tmo3/txd2-a/sda0/irq3-b p14/po15/mtioc3a/tmri2/irq4-b/usb0_ovrcura/usb0_dpupe-b pllvss p16/po14/mtioc3c/tmo2/irq6-b/usb 0_vbus/usb0_ovrcurb/usb0_vbusen-b pllvcc p20/po0/mtioc1a/tmri0/txd0/usb0_id p21/po1/mtioc1b/tmci0/rxd0/usb0_exicen p22/po2/mtioc3b/mtclkc-a/tmo0/sck0/usb0_drpd pc3/a19/mtclkf-a/txd5/et_tx_er usb0_dm pe3/d11/poe8# pe5/d13/rspckb-b/irq5 pe6/d14/mosib-b/irq6-a pe7/d15/misob-b/irq7 pa0/a0/bc0#/po16/mtioc6a/ssla1-b pa1/a1/po17/mtioc6b/ssla2-b pa2/a2/po18/mtioc6c/ssla3-b pa3/a3/po19/mtioc6d/et_mdio pa4/a4/po20/mtioc7a/ssla0-b/et_mdc pa5/a5/po21/mtioc7b/rspcka-b/et_linksta pa6/a6/po22/mtioc8a/mosia-b/et_exout pa7/a7/po23/mtioc8b/misoa-b/et_wol vss vcc pb1/a9/po25/mtioc9c/et_erxd0/rmii_rxd0 pb2/a10/po26/mtioc9b/mtclkg-b/et_rx_clk/ref50ck pb3/a11/po27/mtioc9d/mtclkh-b/et_rx_er/rmii_rx_er pb4/a12/po28/mtioc10a/mtclke-b/et_tx_en/rmii_txd_en pb5/a13/po29/mtioc10c/mtclkf-b/et_etxd0/rmii_txd0 pb6/a14/po30/mtioc10b/et_etxd1/rmii_txd1 pb7/a15/po31/mtioc10d/et_crs/rmii_crs_dv pc0/a16/mtclkg-a/ssla1-a/et_erxd3 pc1/a17/mtclkh-a/sck5/ssla2-a/et_erxd2 pe4/d12/sslb0-b pb0/a8/po24/mtioc9a/et_erxd1/rmii_rxd1 vcc vss mde vcl md1 md0 res# xtal vss extal p35/nmi p34/po12/mtioc0a/tmci3/sck6/irq4-a/trst# p33/po11/mtioc0d/rxd6/crx0/irq3-a p32/po10/mtioc0c/txd6/ctx0/irq2-a/rtcout p31/po9/mtioc4d-a/tmci2/sslb0-a/irq1/tms p30/po8/mtioc4b-a/tmri3/rxd1/misob-a/irq0/tdi p27/cs7#/po7/mtioc2b/sck1/rspckb-a/tck p26/cs6#/po6/mtioc2a/tmo1/txd1/mosib-a/tdo p25/cs5#/adtrg0#-b/po5/mtio c4c/mtclkb-a/rxd3/usb0_dprpd p23/po3/mtioc3d/mtclkd-a/txd3/usb0_dpupe-a emle vcc pe2/d10/sslb3-b/poe9# p05/da1/irq13-a p24/cs4#/po4/mtioc4a/mtclka- a/tmri1/sck3/usb0_vbusen-a RX62N group rx621 group plqp0100kb-a (100-pin lqfp) (top view) xcin xcout
r01ds0052ej0110 rev.1.10 page 15 of 146 feb 10, 2011 RX62N group, rx62 1 group 1. overview figure 1.8 pin assignment of th e 100-pin lqfp (a ssistance diagram) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 p31/po9/mtioc4d-a/tmci2/sslb0-a/irq1/tms 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 pe0/d8/sslb1-b pd7/d7/mtic5u/poe0# pd6/d6/mtic5v/poe1# pd5/d5/mtic5w/poe2# pd4/d4/mtic11u-b/poe3# pd3/d3/mtic11v-b/poe4# pd2/d2/mtic11w-b/poe5# pd1/d1/poe6# pd0/d0/poe7# p47/an7/irq15-b p46/an6/irq14 p45/an5/irq13-b p43/an3/irq11 p42/an2/irq10 p41/an1/irq9 vrefl p40/an0/irq8 vrefh avcc p07/adtrg0#-a/irq15-a avss pe1/d9/sslb2-b p44/an4/irq12 vcc vss mde vcl md1 md0 res# xtal vss extal p34/po12/mtioc0a/tmci3/sck6/irq4-a/trst# p30/po8/mtioc4b-a/tmri3/rxd1/misob-a/irq0/tdi p27/cs7#/po7/mtioc2b/sck1/rspckb-a/tck p26/cs6#/po6/mtioc2a/tmo1/txd1/mosib-a/tdo p25/cs5#/adtrg0#-b/po5/mtioc4c/mtclkb-a/rxd3/usb0_dprpd p23/po3/mtioc3d/mtclkd-a/txd3/usb0_dpupe-a emle vcc pe2/d10/sslb3-b/poe9# p05/da1/irq13-a p24/cs4#/po4/mtioc4a/mtclka-a/tmri1/sck3/usb0_vbusen-a 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 pc2/a18/mtclke-a/rxd5/ssla3-a/et_rx_dv pc4/a20/cs3#/mtclkc-b/ssla0-a/et_tx_clk pc5/a21/cs2#/wait#-c/mtic11w-a/mtclkd-b/rspcka-a/et_etxd2 pc6/a22/cs1#/mtic11v-a/mtclka-b/mosia-a/et_etxd3 pc7/a23/cs0#/mtic11u-a/mtclkb-b/misoa-a/et_col p50/wr0#/wr#/txd2-b/sslb1-a p51/wr1#/bc1#/wait#-d/sck2/sslb2-a p52/rd#/rxd2-b/sslb3-a p53/bclk p54/mtioc4b-b p55/wait#-b/mtioc4d-b vss_usb usb0_dp vcc_usb p12/tmci1/rxd2-a/scl0/irq2-b p13/adtrg1#/po13/mtioc0b/tmo3/txd2-a/sda0/irq3-b p14/po15/mtioc3a/tmri2/irq4-b/usb0_ovrcura/usb0_dpupe-b pllvss p16/po14/mtioc3c/tmo2/irq6-b/usb0_vbus/usb0_ovrcurb/usb0_vbusen-b pllvcc p20/po0/mtioc1a/tmri0/txd0/usb0_id p21/po1/mtioc1b/tmci0/rxd0/usb0_exicen p22/po2/mtioc3b/mtclkc-a/tmo0/sck0/usb0_drpd pc3/a19/mtclkf-a/txd5/et_tx_er usb0_dm pe3/d11/poe8# pe5/d13/rspckb-b/irq5 pe6/d14/mosib-b/irq6-a pe7/d15/misob-b/irq7 pa0/a0/bc0#/po16/tioc6a/ssla1-b pa1/a1/po17/mtioc6b/ssla2-b pa2/a2/po18/mtioc6c/ssla3-b pa3/a3/po19/mtioc6d/et_mdio pa4/a4/po20/mtioc7a/ssla0-b/et_mdc pa5/a5/po21/mtioc7b/rspcka-b/et_linksta pa6/a6/po22/mtioc8a/mosia-b/et_exout pa7/a7/po23/mtioc8b/misoa-b/et_wol vss vcc pb1/a9/po25/mtioc9c/et_erxd0/rmii_rxd0 pb2/a10/po26/mtioc9b/mtclkg-b/et_rx_clk/ref50ck pb3/a11/po27/mtioc9d/mtclkh-b/et_rx_er/rmii_rx_er pb4/a12/po28/mtioc10a/mtclke-b/et_tx_en/rmii_txd_en pb5/a13/po29/mtioc10c/mtclkf-b/et_etxd0/rmii_txd0 pb6/a14/po30/mtioc10b/et_etxd1/rmii_txd1 pb7/a15/po31/mtioc10d/et_crs/rmii_crs_dv pc0/a16/mtclkg-a/ssla1-a/et_erxd3 pc1/a17/mtclkh-a/sck5/ssla2-a/et_erxd2 pe4/d12/sslb0-b pb0/a8/po24/mtioc9a/et_erxd1/rmii_rxd1 p35/nmi p32/po10/mtioc0c/txd6/ctx0/irq2-a/rtcout p33/po11/mtioc0d/rxd6/crx0/irq3-a RX62N group rx621 group plqp0100kb-a (100-pin lqfp) (top view) xcin xcout
r01ds0052ej0110 rev.1.10 page 16 of 146 feb 10, 2011 RX62N group, rx62 1 group 1. overview figure 1.9 pin assignment of the 85-pin tflga RX62N group rx621 group ptlg0085ja-a (85-pin tflga) (upper perspective view) p 0 5 a v c c v r e f l p 4 3 p 4 7 p d 1 p d 4 v c c a v s s v r e f h p 4 2 p 4 6 p d 0 p d 2 p 0 3 v s s p 4 0 p 4 1 p 4 4 p 4 5 m d 1 m d e e m l e m d 0 r e s # x c i n x c o u t p 3 4 x t a l e x t a l p 3 2 p 3 5 p 3 3 p 2 7 p 3 1 p 3 0 p 2 6 p l l v c c p 1 4 p 1 3 p 5 3 p 2 5 p 2 3 p 2 4 p 1 6 v c c _ u s b u s b 0 _ d m p 5 2 p 2 1 p 2 2 p 2 0 p l l v s s p 1 2 u s b 0 _ d p v s s _ u s b 10 9 8 7 6 5 4 3 2 1 10 9 8 7 6 5 4 3 2 1 bcdefghj k a bcdefghj k a p d 5 p d 7 p d 6 p d 3 p a 3 p a 1 b s c a n p p a 5 p a 0 v c l p a 6 p a 2 v s s p b 0 p a 4 v c c p b 2 p a 7 p b 3 p b 5 p b 1 p b 6 p b 7 p b 4 p 5 1 p c 3 p c 0 p 5 0 p c 2 p c 1
r01ds0052ej0110 rev.1.10 page 17 of 146 feb 10, 2011 RX62N group, rx62 1 group 1. overview table 1.4 list of pins and pin fu nctions (176-pin lfbga) (1 / 6) pin no. power supply clock system control i/o port external bus exdmac etherc edmac usb timers (mtu, tmr, ppg, poe, wdt) communi- cation (sci, can, rspi, riic) others 176-pin lfbga a1 avss a2 avcc a3 p42 irq10-b/an2 a4 p45 irq13-b/an5 a5 p46 irq14/an6 a6 p90 d16/a16-b a7 pd0 d0 poe7# a8 pd2 d2 mtic11w-b/ poe5# a9 pd3 d3 mtic11v-b/ poe4# a10 pd4 d4 mtic11u-b/ poe3# a11 pg0 d24 a12 pd7 d7 mtic5u-b/ poe0# a13 p61 cs1#-a/ sdcs# a14 p63 cs3#-a/ cas# a15 pe1 d9 sslb2-b b1 p02 tmci1-a sck6-a irq10-a b2 vrefh b3 vrefl b4 p44 irq12/an4 b5 p47 irq15-b/an7 b6 p91 d17/a17-b b7 pd1 d1 poe6# b8 p96 d22/a22-b b9 p97 d23/a23-b b10 pd6 d6 mtic5v-b/ poe1# b11 p60 cs0#-a b12 p62 cs2#-a/ ras# b13 p64 cs4#-a/ we# b14 pe2 d10 poe9# sslb3-b b15 sdclk p70 c1 p00 tmri0-a txd6-a irq8-a c2 p03 irq11-a/da0 c3 p05 irq13-a/da1 c4 p07 irq15-a/ adtrg0#-a c5 p40 irq8-b/an0
r01ds0052ej0110 rev.1.10 page 18 of 146 feb 10, 2011 RX62N group, rx62 1 group 1. overview c6 vcc c7 p92 d18/a18-b c8 p94 d20/a20-b c9 vcc c10 pd5 d5 mtic5w-b/ poe2# c11 vcc c12 pe0 d8 sslb1-b c13 pe3 d11 poe8# c14 pe5 d13 rspckb-b irq5-a c15 pe6 d14 mosib-b irq6-a d1 emle d2 p01 tmci0-a rxd6-a irq9-a d3 vcc d4 p41 irq9-b/an1 d5 p43 irq11-b/an3 d6 vss d7 p93 d19/a19-b d8 p95 d21/a21-b d9 vss d10 pg1 d25 d11 vss d12 vss d13 pe4 d12 sslb0-b d14 pe7 d15 misob-b irq7-a d15 p65 cs5#-a/ cke e1 xcin e2 cnvss e3 bscanp e4 vss e12 pg2 d26 trdata0 e13 vcc e14 p66 cs6#-a/ dqm0 e15 p67 cs7#-a/ dqm1 f1 xcout f2 wdtovf# f3 vcl f4 vss f12 pg4 d28 trsync f13 pg3 d27 trdata1 f14 pa0 a0/bc0#/ dqm2 mtioc6a/ po16 ssla1-b table 1.4 list of pins and pin fu nctions (176-pin lfbga) (2 / 6) pin no. power supply clock system control i/o port external bus exdmac etherc edmac usb timers (mtu, tmr, ppg, poe, wdt) communi- cation (sci, can, rspi, riic) others 176-pin lfbga
r01ds0052ej0110 rev.1.10 page 19 of 146 feb 10, 2011 RX62N group, rx62 1 group 1. overview f15 pg5 d29 trclk g1 vss g2 md1 g3 md0 g4 mde g12 vss g13 vcc g14 pg6 d30 trdata2 g15 pa1 a1/dqm3 mtioc6b/ po17 ssla2-b h1 xtal h2 p35 nmi h3 vcc h4 res# h12 pg7 d31 trdata3 h13 pa2 a2 mtioc6c/ po18 ssla3-b h14 pa4 a4 mtioc7a/ po20 ssla0-b h15 pa3 a3 mtioc6d/ po19 j1 extal j2 p32 mtioc0c/ po10/ rtcout ctx0/ txd6-b irq2-a j3 pf3 tms j4 p34 mtioc0a/ tmci3-b/ po12 sck6-b irq4-a j12 vss j13 pa5 a5 mtioc7b/ po21 rspcka-b j14 pa7 a7 mtioc8b/ po23 misoa-b j15 pa6 a6 mtioc8a/ po22 mosia-b k1 p33 mtioc0d/ po11 crx0/ rxd6-b irq3-a k2 p31 usb1_dprpd mtioc4d-a/ tmci2-b/ po9 sslb0-a irq1-a k3 pf0 txd1-b tdo k4 pf4 trst# k12 pb1 a9 mtioc9c/ po25 k13 p71 cs1#-b et_mdio k14 p72 cs2#-b et_mdc table 1.4 list of pins and pin fu nctions (176-pin lfbga) (3 / 6) pin no. power supply clock system control i/o port external bus exdmac etherc edmac usb timers (mtu, tmr, ppg, poe, wdt) communi- cation (sci, can, rspi, riic) others 176-pin lfbga
r01ds0052ej0110 rev.1.10 page 20 of 146 feb 10, 2011 RX62N group, rx62 1 group 1. overview k15 pb0 a8 mtioc9a/ po24 l1 pf2 rxd1-b tdi l2 p27 cs7#-c usb1_exicen mtioc2b/ po7 rspckb-a/ sck1-a l3 vcc l4 p30 usb1_drpd mtioc4b-a/ tmri3-b/ po8 misob-a/ rxd1-a irq0-a l12 vss l13 pb4 a12 mtioc10a/ mtclke-b/ po28 l14 pb3 a11 mtioc9d/ mtclkh-b/ po27 l15 vcc m1 pf1 sck1-b tck m2 p25 cs5#-c/ edack1-b usb0_dprpd mtioc4c-a/ mtclkb-a/ po5 rxd3-b adtrg0#-b m3 p22 edreq0-b usb0_drpd mtioc3b-a/ mtclkc-a/ tmo0/ po2 sck0 m4 vss m5 p11 usb1_vbusen -a mtic5v-a/ tmci3-a sck2-a irq1-b m6 p55 wait#-b/ edreq0-c et_exout mtioc4d-b m7 p54 edack0-c et_linksta mtioc4b-b m8 p51 wr1#/ bc1#/ wait#-d sslb2-a/ sck2-b m9 vss m10 pc6 a22-a/ cs1#-c et_etxd3 mtic11v-a/ mtclka-b mosia-a m11 p81 edack0-a et_etxd0/ rmii_txd0 mtioc3d-b m12 pc0 a16-a et_erxd3 mtclkg-a ssla1-a m13 vcc m14 pb6 a14 mtioc10b/ po30 m15 pb2 a10 mtioc9b/ mtclkg-b/ po26 n1 p26 cs6#-c usb1_id mtioc2a/ tmo1/ po6 mosib-a/ txd1-a table 1.4 list of pins and pin fu nctions (176-pin lfbga) (4 / 6) pin no. power supply clock system control i/o port external bus exdmac etherc edmac usb timers (mtu, tmr, ppg, poe, wdt) communi- cation (sci, can, rspi, riic) others 176-pin lfbga
r01ds0052ej0110 rev.1.10 page 21 of 146 feb 10, 2011 RX62N group, rx62 1 group 1. overview n2 p23 edack0-b usb0_dpupe- a mtioc3d-a/ mtclkd-a/ po3 txd3-b n3 p20 usb0_id mtioc1a/ tmri0-b/ po0 sda1/ txd0 n4 p17 usb1_vbus/ usb1_ovrcu rb/ usb1_vbusen -b mtioc3a/ po15 txd3-a irq7-b n5 p15 usb1_ovrcu ra/ usb1_dpupe- b mtioc0b/ tmci2-a/ po13 sck3-a irq5-b n6 p57 wait#-a/ wr3#/ bc3#/ edreq1-c n7 p10 usb1_dpupe- a mtic5w-a/ tmri3-a irq0-b n8 p52 rd# sslb3-a/ rxd2-b n9 vcc n10 pc5 a21-a/ cs2#-c/ wait#-c et_etxd2 mtic11w-a/ mtclkd-b rspcka-a n11 pc3 a19-a et_tx_er mtclkf-a txd5 n12 pc2 a18-a et_rx_dv mtclke-a ssla3-a/ rxd5 n13 p74 cs4#-b et_erxd1/ rmii_rxd1 n14 p73 cs3#-b et_wol n15 pb5 a13 mtioc10c/ mtclkf-b/ po29 p1 p24 cs4#-c/ edreq1-b usb0_vbusen -a mtioc4a-a/ mtclka-a/ tmri1/ po4 sck3-b p2 pllvcc p3 p16 usb0_vbus/ usb0_ovrcu rb/ usb0_vbusen -b mtioc3c-a/ tmo2/ po14 rxd3-a irq6-b p4 p14 usb0_ovrcu ra/ usb0_dpupe- b tmri2 irq4-b p5 p13 tmo3 sda0/ txd2-a irq3-b/ adtrg1# p6 vcc_usb table 1.4 list of pins and pin fu nctions (176-pin lfbga) (5 / 6) pin no. power supply clock system control i/o port external bus exdmac etherc edmac usb timers (mtu, tmr, ppg, poe, wdt) communi- cation (sci, can, rspi, riic) others 176-pin lfbga
r01ds0052ej0110 rev.1.10 page 22 of 146 feb 10, 2011 RX62N group, rx62 1 group 1. overview p7 p56 wr2#/ bc2#/ edack1-c mtioc3c-b p8 vcc_usb p9 p84 p10 p50 wr0#/ wr# sslb1-a/ txd2-b p11 p82 edreq1-a et_etxd1/ rmii_txd1 mtioc4a-b p12 pc4 a20-a/ cs3#-c et_tx_clk mtclkc-b ssla0-a p13 p76 cs6#-b et_rx_clk/ ref50ck p14 pc1 a17-a et_erxd2 mtclkh-a ssla2-a/ sck5 p15 pb7 a15 mtioc10d/ po31 r1 p21 usb0_exicen mtioc1b/ tmci0-b/ po1 scl1/ rxd0 r2 pllvss r3 p12 mtic5u-a/ tmci1-b scl0/ rxd2-a irq2-b r4 usb0_dm r5 usb0_dp r6 vss_usb r7 usb1_dm r8 usb1_dp r9 p85 r10 bclk p53 r11 p83 edack1-a et_crs/ rmii_crs_d v mtioc4c-b r12 pc7 a23-a/ cs0#-b et_col mtic11u-a/ mtclkb-b misoa-a r13 p80 edreq0-a et_tx_en/ rmii_txd_e n mtioc3b-b r14 p77 cs7#-b et_rx_er/ rmii_rx_er r15 p75 cs5#-b et_erxd0/ rmii_rxd0 table 1.4 list of pins and pin fu nctions (176-pin lfbga) (6 / 6) pin no. power supply clock system control i/o port external bus exdmac etherc edmac usb timers (mtu, tmr, ppg, poe, wdt) communi- cation (sci, can, rspi, riic) others 176-pin lfbga
r01ds0052ej0110 rev.1.10 page 23 of 146 feb 10, 2011 RX62N group, rx62 1 group 1. overview table 1.5 list of pins and pin fu nctions (145-pin tflga) (1 / 5) pin no. power supply clock system control i/o port external bus exdmac etherc edmac usb timers (mtu, tmr, ppg, poe, wdt) communi- cation (sci, can, rspi, riic) others 145-pin tflga a1 avss a2 avcc a3 vrefl a4 p42 irq10-b/an2 a5 p44 irq12/an4 a6 p47 irq15-b/an7 a7 p91 a17-b a8 pd0 d0 poe7# a9 pd3 d3 m tic11v-b/ poe4# a10 pd6 d6 m tic5v/ poe1# a11 p60 cs0#-a a12 p62 cs2#-a/ ras# a13 p64 cs4#-a/ we# b1 p03 irq11-a/da0 b2 p07 irq15-a/ adtrg0#-a b3 vrefh b4 p40 irq8-b/an0 b5 p45 irq13-b/an5 b6 p90 a16-b b7 pd1 d1 poe6# b8 pd5 d5 m tic5w/ poe2# b9 vss b10 pe0 d8 sslb1-b b11 pe2 d10 poe9# sslb3-b b12 pe1 d9 sslb2-b b13 pe4 d12 sslb0-b c1 p01 tmci0-a rxd6-a irq9-a c2 p05 irq13-a/da1 c3 vss c4 p41 irq9-b/an1 c5 p46 irq14/an6 c6 p92 a18-b c7 pd2 d2 m tic11w-b/ poe5# c8 pd7 d7 m tic5u/ poe0# c9 p61 cs1#-a/ sdcs#
r01ds0052ej0110 rev.1.10 page 24 of 146 feb 10, 2011 RX62N group, rx62 1 group 1. overview c10 p63 cs3#-a/ cas# c11 pe5 d13 rspckb-b irq5-a c12 pe3 d11 poe8# c13 sdclk p70 d1 emle d2 vcc d3 p02 tmci1-a sck6-a irq10-a d4 p43 irq11-b/an3 d5 vcc d6 vss d7 p93 a19-b d8 pd4 d4 m tic11u-b/ poe3# d9 vcc d10 vss d11 vcc d12 pe7 d15 misob-b irq7-a d13 pe6 d14 mosib-b irq6-a e1 vcl e2 vss e3 p00 tmri0-a txd6-a irq8-a e4 bscanp e5 ?in.c?j e10 p65 cs5#-a/ cke e11 p67 cs7#-a/ dqm1 e12 pa0 a0/bc0# m tioc6a/ po16 ssla1-b e13 p66 cs6#-a/ dqm0 f1 xcin f2 xcout f3 wdtovf# f4 mde f10 pa1 a1 m tioc6b/ po17 ssla2-b f11 pa3 a3 m tioc6d/ po19 f12 vcc f13 pa2 a2 m tioc6c/ po18 ssla3-b g1 xtal g2 vss table 1.5 list of pins and pin fu nctions (145-pin tflga) (2 / 5) pin no. power supply clock system control i/o port external bus exdmac etherc edmac usb timers (mtu, tmr, ppg, poe, wdt) communi- cation (sci, can, rspi, riic) others 145-pin tflga
r01ds0052ej0110 rev.1.10 page 25 of 146 feb 10, 2011 RX62N group, rx62 1 group 1. overview g3 md1 g4 md0 g10 vss g11 pa5 a5 m tioc7b/ po21 rspcka-b g12 pa6 a6 m tioc8a/ po22 mosia-b g13 pa4 a4 m tioc7a/ po20 ssla0-b h1 extal h2 p34 mtioc0a/ tmci3/ po12 sck6-b irq4-a/ trst# h3 vcc h4 res# h10 pb0 a8 m tioc9a/ po24 h11 p71 cs1#-b et_mdio h12 pb1 a9 m tioc9c/ po25 h13 pa7 a7 m tioc8b/ po23 misoa-b j1 p33 mtioc0d/ po11 crx0/ rxd6-b irq3-a j2 p27 cs7#-c m tioc2b/ po7 rspckb-a/ sck1 tck j3 p35 nmi j4 p32 mtioc0c/ po10/ rtcout ctx0/ txd6-b irq2-a j10 pb2 a10 m tioc9b/ m tclkg-b/ po26 j11 pb4 a12 m tioc10a/ m tclke-b/ po28 j12 pb5 a13 m tioc10c/ m tclkf-b/ po29 j13 p72 cs2#-b et_mdc k1 p30 m tioc4b-a/ tmri3/ po8 rxd1/ misob-a irq0/ tdi k2 p24 cs4#-c/ edreq1-b usb0_vbuse n-a m tioc4a-a/ m tclka-a/ tmri1/po4 sck3-b k3 p31 m tioc4d-a/ tmci2-b/ po9 sslb0-a irq1/ tms table 1.5 list of pins and pin fu nctions (145-pin tflga) (3 / 5) pin no. power supply clock system control i/o port external bus exdmac etherc edmac usb timers (mtu, tmr, ppg, poe, wdt) communi- cation (sci, can, rspi, riic) others 145-pin tflga
r01ds0052ej0110 rev.1.10 page 26 of 146 feb 10, 2011 RX62N group, rx62 1 group 1. overview k4 p26 cs6#-c m tioc2a/ tmo1/ po6 mosib-a/ txd1 tdo k5 bclk p53 k6 vss k7 pc7 a23/ cs0#-b et_col m tic11u-a/ m tclkb-b misoa-a k8 p82 edreq1-a et_etxd1/ rmii_txd1 m tioc4a-b trsync k9 pc3 a19-a et_tx_er m tclkf-a txd5 k10 pb7 a15 m tioc10d/ po31 k11 p73 cs3#-b et_wol k12 pc0 a16-a et_erxd3 m tclkg-a ssla1-a k13 pb3 a11 m tioc9d/ m tclkh-b/ po27 l1 p25 cs5#-c/ edack1-b usb0_dprpd m tioc4c-a/ m tclkb-a/ po5 rxd3-b adtrg0#-b l2 p22 edreq0-b usb0_drpd m tioc3b-a/ m tclkc-a/ tmo0/po2 sck0 l3 p17 mtioc3a/ po15 txd3-a irq7-b l4 p12 tmci1-b scl0/ rxd2-a irq2-b l5 vcc_usb l6 p56 edack1-c m tioc3c-b l7 p52 rd# sslb3-a/ rxd2-b l8 p83 edack1-a et_crs/ rmii_crs_d v m tioc4c-b trclk l9 p81 edack0-a et_etxd0/ rmii_txd0 m tioc3d-b trdata1 l10 p77 cs7#-b et_rx_er/ rmii_rx_er l11 p75 cs5#-b et_erxd0/ rmii_rxd0 l12 vcc l13 pb6 a14 m tioc10b/ po30 m1 p23 edack0-b usb0_dpupe -a m tioc3d-a/ m tclkd-a/ po3 txd3-b m2 p20 usb0_id m tioc1a/ tmri0-b/ po0 sda1/ txd0 m3 pllvcc table 1.5 list of pins and pin fu nctions (145-pin tflga) (4 / 5) pin no. power supply clock system control i/o port external bus exdmac etherc edmac usb timers (mtu, tmr, ppg, poe, wdt) communi- cation (sci, can, rspi, riic) others 145-pin tflga
r01ds0052ej0110 rev.1.10 page 27 of 146 feb 10, 2011 RX62N group, rx62 1 group 1. overview m4 p15 mtioc0b/ tmci2-a/ po13 sck3-a irq5-b m5 p14 usb0_ovrc ura/ usb0_dpupe -b tmri2 irq4-b m6 vss_usb m7 p55 wait#-b/ edreq0-c et_exout m tioc4d-b trdata3 m8 p50 wr0#/ wr# sslb1-a/ txd2-b m9 pc6 a22/cs1#-c et_etxd3 m tic11v-a/ m tclka-b mosia-a m10 p80 edreq0-a et_tx_en/ rmii_txd_e n m tioc3b-b trdata0 m11 pc2 a18-a et_rx_dv m tclke-a ssla3-a/ rxd5 m12 pc1 a17-a et_erxd2 m tclkh-a ssla2-a/ sck5 m13 vss n1 p21 usb0_exice n m tioc1b/ tmci0-b/ po1 scl1/rxd0 n2 p16 usb0_vbus/ usb0_ovrc urb/ usb0_vbuse n-b m tioc3c-a/ tmo2/ po14 rxd3-a irq6-b n3 pllvss n4 p13 tmo3 sda0/ txd2-a irq3-b/ adtrg1# n5 usb0_dm n6 usb0_dp n7 p54 edack0-c et_linksta m tioc4b-b trdata2 n8 p51 wr1#/bc1#/ wait#-d sslb2-a/ sck2 n9 vcc n10 pc5 a21/cs2#-c/ wait#-c et_etxd2 m tic11w-a/ m tclkd-b rspcka-a n11 pc4 a20/cs3#-c et_tx_clk m tclkc-b ssla0-a n12 p76 cs6#-b et_rx_clk/ ref50ck n13 p74 cs4#-b et_erxd1/ rmii_rxd1 table 1.5 list of pins and pin fu nctions (145-pin tflga) (5 / 5) pin no. power supply clock system control i/o port external bus exdmac etherc edmac usb timers (mtu, tmr, ppg, poe, wdt) communi- cation (sci, can, rspi, riic) others 145-pin tflga
r01ds0052ej0110 rev.1.10 page 28 of 146 feb 10, 2011 RX62N group, rx62 1 group 1. overview table 1.6 list of pins and pin fu nctions (144-pin lqfp) (1 / 5) pin no. power supply clock system control i/o port external bus exdmac etherc edmac usb timers (mtu, tmr, ppg, poe, wdt) communi- cation (sci, can, rspi, riic) others 144-pin lqfp 1 avss 2p05 irq13-a/da1 3vcc 4p03 irq11-a/da0 5 vss 6 p02 tmci1-a sck6-a irq10-a 7 p01 tmci0-a rxd6-a irq9-a 8 p00 tmri0-a txd6-a irq8-a 9 bscanp 10 emle 11 wdtovf# 12 vss 13 mde 14 vcl 15 md1 16 md0 17 xcin 18 xcout 19 res# 20 xtal 21 vss 22 extal 23 vcc 24 p35 nmi 25 p34 mtioc0a/ tmci3/ po12 sck6-b irq4-a/ trst# 26 p33 mtioc0d/ po11 crx0/ rxd6-b irq3-a 27 p32 mtioc0c/ po10/ rtcout ctx0/ txd6-b irq2-a 28 p31 mtioc4d- a/ tmci2-b/ po9 sslb0-a irq1/ tms 29 p30 mtioc4b-a/ tmri3/ po8 rxd1/ misob-a irq0/ tdi 30 p27 cs7#-c mtioc2b/ po7 rspckb-a/ sck1 tck 31 p26 cs6#-c mtioc2a/ tmo1/ po6 mosib-a/ txd1 tdo
r01ds0052ej0110 rev.1.10 page 29 of 146 feb 10, 2011 RX62N group, rx62 1 group 1. overview 32 p25 cs5#-c/ edack1-b usb0_dprpd mtioc4c- a/ mtclkb-a/ po5 rxd3-b adtrg0#-b 33 p24 cs4#-c/ edreq1-b usb0_vbusen -a mtioc4a-a/ mtclka-a/ tmri1/po4 sck3-b 34 p23 edack0-b usb0_dpupe- a mtioc3d- a/ mtclkd-a/ po3 txd3-b 35 p22 edreq0-b usb0_drpd mtioc3b-a/ mtclkc-a/ tmo0/po2 sck0 36 p21 usb0_exicen mtioc1b/ tmci0-b/ po1 scl1/rxd0 37 p20 usb0_id mtioc1a/ tmri0-b/ po0 sda1/ txd0 38 p17 mtioc3a/ po15 txd3-a irq7-b 39 pllvcc 40 p16 usb0_vbus/ usb0_ovrcu rb/ usb0_vbusen -b mtioc3c- a/ tmo2/ po14 rxd3-a irq6-b 41 pllvss 42 p15 mtioc0b/ tmci2-a/ po13 sck3-a irq5-b 43 p14 usb0_ovrcu ra/ usb0_dpupe- b tmri2 irq4-b 44 p13 tmo3 sda0/ txd2-a irq3-b/ adtrg1# 45 p12 tmci1-b scl0/ rxd2-a irq2-b 46 vcc_usb 47 usb0_dm 48 usb0_dp 49 vss_usb 50 p56 edack1-c mtioc3c-b 51 p55 wait#-b/ edreq0-c et_exout mtioc4d-b trdata3 52 p54 edack0-c et_linksta mtioc4b-b trdata2 53 bclk p53 54 p52 rd# sslb3-a/ rxd2-b table 1.6 list of pins and pin fu nctions (144-pin lqfp) (2 / 5) pin no. power supply clock system control i/o port external bus exdmac etherc edmac usb timers (mtu, tmr, ppg, poe, wdt) communi- cation (sci, can, rspi, riic) others 144-pin lqfp
r01ds0052ej0110 rev.1.10 page 30 of 146 feb 10, 2011 RX62N group, rx62 1 group 1. overview 55 p51 wr1#/bc1#/ wait#-d sslb2-a/ sck2 56 p50 wr0#/ wr# sslb1-a/ txd2-b 57 vss 58 p83 edack1-a et_crs/ rmii_crs_dv mtioc4c-b trclk 59 vcc 60 pc7 a23/ cs0#-b et_col mtic11u-a/ mtclkb-b misoa-a 61 pc6 a22/ cs1#-c et_etxd3 mtic11v-a/ mtclka-b mosia-a 62 pc5 a21/cs2#-c/ wait#-c et_etxd2 mtic11w-a/ mtclkd-b rspcka-a 63 p82 edreq1-a et_etxd1/ rmii_txd1 mtioc4a-b trsync 64 p81 edack0-a et_etxd0/ rmii_txd0 mtioc3d-b trdata1 65 p80 edreq0-a et_tx_en/ rmii_txd_en mtioc3b-b trdata0 66 pc4 a20/cs3#-c et_tx_clk mtclkc-b ssla0-a 67 pc3 a19-a et_tx_er mtclkf-a txd5 68 p77 cs7#-b et_rx_er/ rmii_rx_er 69 p76 cs6#-b et_rx_clk/ ref50ck 70 pc2 a18-a et_rx_dv mtclke-a ssla3-a/ rxd5 71 p75 cs5#-b et_erxd0/ rmii_rxd0 72 p74 cs4#-b et_erxd1/ rmii_rxd1 73 pc1 a17-a et_erxd2 mtclkh-a ssla2-a/ sck5 74 vcc 75 pc0 a16-a et_erxd3 mtclkg-a ssla1-a 76 vss 77 p73 cs3#-b et_wol 78 pb7 a15 mtioc10d/ po31 79 pb6 a14 mtioc10b/ po30 80 pb5 a13 mtioc10c/ mtclkf-b/ po29 81 pb4 a12 mtioc10a/ mtclke-b/ po28 table 1.6 list of pins and pin fu nctions (144-pin lqfp) (3 / 5) pin no. power supply clock system control i/o port external bus exdmac etherc edmac usb timers (mtu, tmr, ppg, poe, wdt) communi- cation (sci, can, rspi, riic) others 144-pin lqfp
r01ds0052ej0110 rev.1.10 page 31 of 146 feb 10, 2011 RX62N group, rx62 1 group 1. overview 82 pb3 a11 mtioc9d/ mtclkh-b/ po27 83 pb2 a10 mtioc9b/ mtclkg-b/ po26 84 pb1 a9 mtioc9c/ po25 85 p72 cs2#-b et_mdc 86 p71 cs1#-b et_mdio 87 pb0 a8 mtioc9a/ po24 88 pa7 a7 mtioc8b/ po23 misoa-b 89 pa6 a6 mtioc8a/ po22 mosia-b 90 pa5 a5 mtioc7b/ po21 rspcka-b 91 vcc 92 pa4 a4 mtioc7a/ po20 ssla0-b 93 vss 94 pa3 a3 mtioc6d/ po19 95 pa2 a2 mtioc6c/ po18 ssla3-b 96 pa1 a1 mtioc6b/ po17 ssla2-b 97 pa0 a0/bc0#/ mtioc6a/ po16 ssla1-b 98 p67 cs7#-a/ dqm1 99 p66 cs6#-a/ dqm0 100 p65 cs5#-a/ cke 101 pe7 d15 misob-b irq7-a 102 pe6 d14 mosib-b irq6-a 103 vcc 104 sdclk p70 105 vss 106 pe5 d13 rspckb-b irq5-a 107 pe4 d12 sslb0-b 108 pe3 d11 poe8# 109 pe2 d10 poe9# sslb3-b 110 pe1 d9 sslb2-b 111 pe0 d8 sslb1-b table 1.6 list of pins and pin fu nctions (144-pin lqfp) (4 / 5) pin no. power supply clock system control i/o port external bus exdmac etherc edmac usb timers (mtu, tmr, ppg, poe, wdt) communi- cation (sci, can, rspi, riic) others 144-pin lqfp
r01ds0052ej0110 rev.1.10 page 32 of 146 feb 10, 2011 RX62N group, rx62 1 group 1. overview 112 p64 cs4#-a/ we# 113 p63 cs3#-a/ cas# 114 p62 cs2#-a/ ras# 115 p61 cs1#-a/ sdcs# 116 vss 117 p60 cs0#-a 118 vcc 119 pd7 d7 mtic5u/ poe0# 120 pd6 d6 mtic5v/ poe1# 121 pd5 d5 mtic5w/ poe2# 122 pd4 d4 mtic11u-b/ poe3# 123 pd3 d3 mtic11v-b/ poe4# 124 pd2 d2 mtic11w-b/ poe5# 125 pd1 d1 poe6# 126 pd0 d0 poe7# 127 p93 a19-b 128 p92 a18-b 129 p91 a17-b 130 vss 131 p90 a16-b 132 vcc 133 p47 irq15-b/an7 134 p46 irq14/an6 135 p45 irq13-b/an5 136 p44 irq12/an4 137 p43 irq11-b/an3 138 p42 irq10-b/an2 139 p41 irq9-b/an1 140 vrefl 141 p40 irq8-b/an0 142 vrefh 143 avcc 144 p07 irq15-a/ adtrg0#-a table 1.6 list of pins and pin fu nctions (144-pin lqfp) (5 / 5) pin no. power supply clock system control i/o port external bus exdmac etherc edmac usb timers (mtu, tmr, ppg, poe, wdt) communi- cation (sci, can, rspi, riic) others 144-pin lqfp
r01ds0052ej0110 rev.1.10 page 33 of 146 feb 10, 2011 RX62N group, rx62 1 group 1. overview table 1.7 list of pins and pin fu nctions (100-pin lqfp) (1 / 4) pin no. power supply clock system control i/o port external bus etherc edmac usb timers (mtu, tmr, ppg, poe) communi- cation (sci, can, rspi, riic) others 100-pin lqfp 1vcc 2emle 3 vss 4mde 5vcl 6md1 7md0 8xcin 9 xcout 10 res# 11 xtal 12 vss 13 extal 14 vcc 15 p35 nmi 16 p34 mtioc0a/ tmci3/ po12 sck6 irq4-a/ trst# 17 p33 mtioc0d/ po11 crx0/ rxd6 irq3-a 18 p32 mtioc0c/ po10/ rtcout ctx0/ txd6 irq2-a 19 p31 mtioc4d- a/ tmci2/ po9 sslb0-a irq1/ tms 20 p30 mtioc4b- a/ tmri3/ po8 rxd1/ misob-a irq0/ tdi 21 p27 cs7# mtioc2b/ po7 rspckb- a/ sck1 tck 22 p26 cs6# mtioc2a/ tmo1/ po6 mosib-a/ txd1 tdo 23 p25 cs5# usb0_dprpd mtioc4c/ mtclkb-a/ po5 rxd3 adtrg0#-b 24 p24 cs4#/ usb0_vbuse n-a mtioc4a/ mtclka/ tmri1/po4 sck3 25 p23 usb0_dpupe- a mtioc3d/ mtclkd-a/ po3 txd3 26 p22 usb0_drpd mtioc3b/ mtclkc-a/ tmo0/po2 sck0
r01ds0052ej0110 rev.1.10 page 34 of 146 feb 10, 2011 RX62N group, rx62 1 group 1. overview 27 p21 usb0_exicen mtioc1b/ tmci0/ po1 rxd0 28 p20 usb0_id mtioc1a/ tmri0/ po0 txd0 29 pllvcc 30 p16 usb0_vbus/ usb0_ovrcu rb/ usb0_vbuse n-b mtioc3c/ tmo2/ po14 irq6-b 31 pllvss 32 p14 usb0_ovrcu ra/ usb0_dpupe- b mtioc3a/ tmri2/ po15 irq4-b 33 p13 mtioc0b/ tmo3/ po13 sda0/ txd2-a irq3-b/ adtrg1# 34 p12 tmci1 scl0/ rxd2-a irq2-b 35 vcc_usb 36 usb0_dm 37 usb0_dp 38 vss_usb 39 p55 wait#-b mtioc4d-b 40 p54 mtioc4b-b 41 bclk p53 42 p52 rd# sslb3-a/ rxd2-b 43 p51 wr1#/bc1#/ wait#-d sslb2-a/ sck2 44 p50 wr0#/ wr# sslb1-a/ txd2-b 45 pc7 a23/ cs0# et_col mtic11u-a/ mtclkb-b misoa-a 46 pc6 a22/ cs1# et_etxd3 mtic11v-a/ mtclka-b mosia-a 47 pc5 a21/cs2#/ wait#-c et_etxd2 mtic11w- a/ mtclkd-b rspcka-a 48 pc4 a20/cs3# et_tx_clk mtclkc-b ssla0-a 49 pc3 a19 et_tx_er mtclkf-a txd5 50 pc2 a18 et_rx_dv mtclke-a ssla3-a/ rxd5 51 pc1 a17 et_erxd2 mtclkh-a ssla2-a/ sck5 52 pc0 a16 et_erxd3 mtclkg-a ssla1-a table 1.7 list of pins and pin fu nctions (100-pin lqfp) (2 / 4) pin no. power supply clock system control i/o port external bus etherc edmac usb timers (mtu, tmr, ppg, poe) communi- cation (sci, can, rspi, riic) others 100-pin lqfp
r01ds0052ej0110 rev.1.10 page 35 of 146 feb 10, 2011 RX62N group, rx62 1 group 1. overview 53 pb7 a15 et_crs/ rmii_crs_d v mtioc10d/ po31 54 pb6 a14 et_etxd1/ rmii_txd1 mtioc10b/ po30 55 pb5 a13 et_etxd0/ rmii_txd0 mtioc10c/ mtclkf-b/ po29 56 pb4 a12 et_tx_en/ rmii_txd_e n mtioc10a/ mtclke-b/ po28 57 pb3 a11 et_rx_er/ rmii_rx_er mtioc9d/ mtclkh-b/ po27 58 pb2 a10 et_rx_clk/ ref50ck mtioc9b/ mtclkg-b/ po26 59 pb1 a9 et_erxd0/ rmii_rxd0 mtioc9c/ po25 60 vcc 61 pb0 a8 et_erxd1/ rmii_rxd1 mtioc9a/ po24 62 vss 63 pa7 a7 et_wol mtioc8b/ po23 misoa-b 64 pa6 a6 et_exout mtioc8a/ po22 mosia-b 65 pa5 a5 et_linksta mtioc7b/ po21 rspcka-b 66 pa4 a4 et_mdc mtioc7a/ po20 ssla0-b 67 pa3 a3 et_mdio mtioc6d/ po19 68 pa2 a2 mtioc6c/ po18 ssla3-b 69 pa1 a1 mtioc6b/ po17 ssla2-b 70 pa0 a0/bc0# mtioc6a/ po16 ssla1-b 71 pe7 d15 misob-b irq7 72 pe6 d14 mosib-b irq6-a 73 pe5 d13 rspckb-b irq5 74 pe4 d12 sslb0-b 75 pe3 d11 poe8# 76 pe2 d10 poe9# sslb3-b 77 pe1 d9 sslb2-b 78 pe0 d8 sslb1-b 79 pd7 d7 mtic5u/ poe0# table 1.7 list of pins and pin fu nctions (100-pin lqfp) (3 / 4) pin no. power supply clock system control i/o port external bus etherc edmac usb timers (mtu, tmr, ppg, poe) communi- cation (sci, can, rspi, riic) others 100-pin lqfp
r01ds0052ej0110 rev.1.10 page 36 of 146 feb 10, 2011 RX62N group, rx62 1 group 1. overview 80 pd6 d6 mtic5v/ poe1# 81 pd5 d5 mtic5w/ poe2# 82 pd4 d4 mtic11u-b/ poe3# 83 pd3 d3 mtic11v-b/ poe4# 84 pd2 d2 mtic11w- b/ poe5# 85 pd1 d1 poe6# 86 pd0 d0 poe7# 87 p47 irq15-b/an7 88 p46 irq14/an6 89 p45 irq13-b/an5 90 p44 irq12/an4 91 p43 irq11/an3 92 p42 irq10/an2 93 p41 irq9/an1 94 vrefl 95 p40 irq8/an0 96 vrefh 97 avcc 98 p07 irq15-a/ adtrg0#-a 99 avss 100 p05 da1/irq13-a table 1.7 list of pins and pin fu nctions (100-pin lqfp) (4 / 4) pin no. power supply clock system control i/o port external bus etherc edmac usb timers (mtu, tmr, ppg, poe) communi- cation (sci, can, rspi, riic) others 100-pin lqfp
r01ds0052ej0110 rev.1.10 page 37 of 146 feb 10, 2011 RX62N group, rx62 1 group 1. overview table 1.8 list of pins and pin fu nctions (85-pin tflga) (1 / 3) pin no. power supply clock system control i/o port external bus usb timers (mtu, tmr, ppg) communi- cation (sci, can, rspi, riic) others 85-pin tflga a1 p05 da1/ irq13- a a2 avcc a3 vrefl a4 p43 irq11- b/an3 a5 p47 irq15/ an7 a6 pd1 d1 a7 pd4 d4 mtic11u a8 pd5 d5 mtic5w a9 pd7 d7 mtic5u a10 pd6 d6 mtic5v b1 vcc b2 avss b3 vrefh b4 p42 irq10/ an2 b5 p46 irq14/ an6 b6 pd0 d0 b7 pd2 d2 mtic11w b8 pd3 d3 mtic11v b9 pa3 a3 mtioc6d/po19 b10 pa1 a1 mtioc6b/po17 ssla2 c1 p03 irq11- a/da0 c2 vss c3 p40 irq8/ an0 c4 p41 irq9/ an1 c5 p44 irq12/ an4 c6 p45 irq13- b/an5 c7 md1 c8 bscanp c9 pa5 a5 mtioc7b/po21 rspcka c10 pa0 a0 mtioc6a/po16 ssla1 d1 mde d2 emle d3 md0 d4 res#
r01ds0052ej0110 rev.1.10 page 38 of 146 feb 10, 2011 RX62N group, rx62 1 group 1. overview d8 vcl d9 pa6 a6 mtioc8a/po22 mosia d10 pa2 a2 mtioc6c/po18 ssla3 e1 xcin e2 xcout e3 p34 mtioc0a/tmci3/po12 sck6 irq4-a/ trst# e8 vss e9 pb0 a8 mtioc9a/po24 e10 pa4 a4 mtioc7a/po20 ssla0 f1 xtal f2 extal f3 p32 mtioc0c/po10/rtcout txd6/ctx0 irq2-a f8 vcc f9 pb2 a10 mtioc9b/mtclkg-b/ po26 f10 pa7 a7 mtioc8b/po23 misoa g1 p35 nmi g2 p33 mtioc0d/po11 rxd6/crx0 irq3-a g3 p27 cs7# mtioc2b/po7 sck1/rspckb tck g8 pb3 a11 mtioc9d/mtclkh-b/po27 g9 pb5 a13 mtioc10c/mtclkf-b/po29 g10 pb1 a9 mtioc9c/po25 h1 p31 mtioc4d/tmci2/po9 sslb0 irq1/ tms h2 p30 mtioc4b/tmri3/po8 rxd1/misob irq0/ tdi h3 p26 cs6# mtioc2a/tmo1/po6 txd1/mosib tdo h4 pllvcc h5 p14 usb0_ovrcur a/usb0_dpupe- b mtioc3a/tmri2/po15 irq4-b h6 p13 mtioc0b/tmo3/po13 txd2-a/sda0 irq3-b/ adtrg 1# h7 bclk p53 h8 pb6 a14 mtioc10b/po30 h9 pb7 a15 mtioc10d/po31 h10 pb4 a12 mtioc10a/mtclke-b/po28 j1 p25 cs5# usb0_dprpd mtioc4c/mtclkb/po5 rxd3 adtrg 0# j2 p23 usb0_dpupe-a mtioc3d/mtclkd/po3 txd3 j3 p24 cs4# usb0_vbusen- a mtioc4a/mtclka-a/tmri1/ po4 sck3 table 1.8 list of pins and pin fu nctions (85-pin tflga) (2 / 3) pin no. power supply clock system control i/o port external bus usb timers (mtu, tmr, ppg) communi- cation (sci, can, rspi, riic) others 85-pin tflga
r01ds0052ej0110 rev.1.10 page 39 of 146 feb 10, 2011 RX62N group, rx62 1 group 1. overview j4 p16 usb0_vbus/ usb0_ovrcur b/ usb0_vbusen- b mtioc3c/tmo2/po14 irq6 j5 vcc_usb j6 usb0_dm j7 p52 rd# rxd2-b/sslb3 j8 p51 wait# sck2/sslb2 j9 pc3 a19 mtclkf-a txd5 j10 pc0 a16 mtclkg-a k1 p21 usb0_exicen mtioc1b/tmci0/po1 rxd0/scl1 k2 p22 usb0_drpd mtioc3b/mtclkc/tmo0/po2 sck0 k3 p20 usb0_id mtioc1a/tmri0/po0 txd0/sda1 k4 pllvss k5 p12 tmci1 rxd2-a/scl0 irq2-b k6 usb0_dp k7 vss_usb k8 p50 wr0# txd2-b/sslb1 k9 pc2 a18 mtclke-a rxd5 k10 pc1 a17 mtclkh-a sck5 table 1.8 list of pins and pin fu nctions (85-pin tflga) (3 / 3) pin no. power supply clock system control i/o port external bus usb timers (mtu, tmr, ppg) communi- cation (sci, can, rspi, riic) others 85-pin tflga
r01ds0052ej0110 rev.1.10 page 40 of 146 feb 10, 2011 RX62N group, rx62 1 group 1. overview 1.5 pin functions table 1.8 lists the pin functions. table 1.9 pin functions (1 / 7) classifications pin name i/o description power supply vcc input power supply pin. connect it to the system power supply. vcl input connect this pin to vss via a 0.1- ? f capacitor. the capacitor should be placed cl ose to the pin. vss input ground pin. connect it to the system power supply (0 v). pllvcc input power supply pin for the p ll circuit. connect it to the system power supply. pllvss input ground pin for the pll circuit. clock xtal output pins for a crystal resona tor. an external clock signal can be input through the extal pin. extal input bclk output outputs the external bus clock for external devices. sdclk output outputs the clock dedicated for the sdram. xcout output input/output pins for the subclock generation circuit. connect a crystal resonator between xcout and xcin. xcin input operating mode control md0, md1, mde input pins for setti ng the operating mode. the signal levels on these pins must not be changed during operation. system control res# input reset signal input pin. this lsi enters the reset state when this signal goes low. emle input input pin to enable the connection of the on-chip emulator signal. when the on-chip emulator is used, this pin should be driven high. when not used, it should be driven low. bscanp input boundary scan pin. boundar y scan is enabled when this pin goes high. when not used, it should be driven low. cnvss cnvss input connect this pin to vss via pull-down resister. on-chip emulator trst# input on-chip emulator pins or boundary scan pins. when the emle pin is driven high, these pins are dedicated for the on-chip emulator. tms input tdi input tck input tdo output trclk output this pin outputs the clock for synchronization with the trace data. trsync output this pin indicates that output from the trdata0 to trdata3 pins is valid. trdata0-a/trdata3-b output these pins output the trace information. address bus a0 to a15 a16-a/a16-b to a23-a/a23-b output output pins for the address. data bus d0 to d31 i/o input and output pins for the bidirectional data bus.
r01ds0052ej0110 rev.1.10 page 41 of 146 feb 10, 2011 RX62N group, rx62 1 group 1. overview bus control rd# output strobe signal which indicates that reading from the external bus interface space is in progress. wr# output strobe signal which indicates that writing to the external bus interface space is in progress, in 1-write strobe mode. wr0# to wr3# output strobe signals which indicate that any group of data bus pins (d7 to d0, d15 to d8, d23 to d16, and d31 to d24) is valid in writing to the external bus interface space, in byte strobe mode. bc0# to bc3# output strobe signals which indicate that any group of data bus pins (d7 to d0, d15 to d8, d23 to d16, and d31 to d24) is valid in access to the external bus interface space, in 1-write strobe mode. we# output output pin for sdram write enable signals. cas# output output pin for sdram column address strobe signals. ras# output output pin for sdram row address strobe signals. cke output output pin for sdram clock enable signals. dqm0 to dqm34 output output pins fo r sdram i/o data mask enable signals. sdcs# output output pin for sdram chip select signals. cs0#-a/cs0#-b cs1#-a/cs1#-b/cs1#-c cs2#-a/cs2#-b/cs2#-c cs3#-a/cs3#-b/cs3#-c cs4#-a/cs4#-b/cs4#-c cs5#-a/cs5#-b/cs5#-c cs6#-a/cs6#-b/cs6#-c cs7#-a/cs7#-b/cs7#-c output select signals for areas 0 to 7. wait#-a/wait#-b/ wait#-c/wait#-d input input pins for wait request signa ls in access to the external space. exdma controller edreq0-a/edreq0-b/ edreq0-c input input pins for external requests of channel 0. edreq1-a/edreq1-b/ edreq1-c input input pins for external requests of channel 1. edack0-a/edack0-b/ edack0-c output output pins for single addr ess transfer acknowledge signals of channel 0. edack1-a/edack1-b/ edack1-c output output pins for single addr ess transfer acknowledge signals of channel 1. interrupt nmi input non-maskable interrupt request signal. irq0-a/irq0-b irq1-a/irq1-b irq2-a/irq2-b irq3-a/irq3-b irq4-a/irq4-b irq5-a/irq5-b irq6-a/irq6-b irq7-a/irq7-b irq8-a/irq8-b irq9-a/irq9-b irq10-a/irq10-b irq11-a/irq11-b irq12 irq13-a/irq13-b irq14 irq15-a/irq15-b input interrupt request signals. table 1.9 pin functions (2 / 7) classifications pin name i/o description
r01ds0052ej0110 rev.1.10 page 42 of 146 feb 10, 2011 RX62N group, rx62 1 group 1. overview multi-function timer pulse unit mtioc0a mtioc0b mtioc0c mtioc0d i/o the tgra0 to tgrd0 input capture input/output compare output/pwm output pins. mtioc1a mtioc1b i/o the tgra1 and tgrb1 input capture input/output compare output/pwm output pins. mtioc2a mtioc2b i/o the tgra2 and tgrb2 input capture input/output compare output/pwm output pins. mtioc3a mtioc3b-a/mtioc3b-b mtioc3c-a/mtioc3c-b mtioc3d-a/mtioc3d-b i/o the tgra3 to tgrd3 input capture input/output compare output/pwm output pins. mtioc4a-a/mtioc4a-b mtioc4b-a/mtioc4b-b mtioc4c-a/mtioc4c-b mtioc4d-a/mtioc4d-b i/o the tgra4 and tgrb4 input capture input/output compare output/pwm output pins. mtic5u-a/mtic5u-b mtic5v-a/mtic5v-b mtic5w-a/mtic5w-b input the tgru5, tgrv5, and tgrw5 input capture input/dead time compensation input pins. mtioc6a mtioc6b mtioc6c mtioc6d i/o the tgra6 to tgrd6 input capture input/output compare output/pwm output pins. mtioc7a mtioc7b i/o the tgra7 and tgrb7 input capture input/output compare output/pwm output pins. mtioc8a mtioc8b i/o the tgra8 and tgrb8 input capture input/output compare output/pwm output pins. mtioc9a mtioc9b mtioc9c mtioc9d i/o the tgra9 to tgrd9 input capture input/output compare output/pwm output pins. mtioc10a mtioc10b mtioc10c mtioc10d i/o the tgra10 to tgrb10 input capture input/output compare output/pwm output pins. mtic11u-a/mtic11u-b mtic11v-a/mtic11v-b mtic11w-a/mtic11w-b input the tgru11, tgrv11, and tgrw11 input capture input/dead time compensation input pins. mtclka-a/mtclka-b mtclkb-a/mtclkb-b mtclkc-a/mtclkc-b mtclkd-a/mtclkd-b mtclke-a/mtclke-b mtclkf-a/mtclkf-b mtclkg-a/mtclkg-b mtclkh-a/mtclkh-b input input pins for external clock signals. port output enable poe0# to poe9# input input pins fo r request signals to place t he mtu large-current pin in the high impedance state. programmable pulse generator po0 to po31 output output pins for the pulse signals. table 1.9 pin functions (3 / 7) classifications pin name i/o description
r01ds0052ej0110 rev.1.10 page 43 of 146 feb 10, 2011 RX62N group, rx62 1 group 1. overview 8-bit timer tmo0 to tmo3 output output pins for the compare match signals. tmci0-a/tmci0-b tmci1-a/tmci1-b tmci2-a/tmci2-b tmci3-a/tmci3-b input input pins for the external clock signals that drive for the counters. tmri0-a/tmri0-b tmri1 tmri2 tmri3-a/tmri3-b input input pins for the counter-reset signals. watchdog timer wdtovf# output output pin for t he counter-overflow signal in watchdog-timer mode. serial communications interface txd0 txd1-a/txd1-b txd2-a/txd2-b txd3-a/txd3-b txd5 txd6-a/txd6-b output output pins for data transmission. rxd0 rxd1-a/rxd1-b rxd2-a/rxd2-b rxd3-a/rxd3-b rxd5 rxd6-a/rxd6-b input input pins for data reception. sck0 sck1-a/sck1-b sck2-a/sck2-b sck3-a/sck3-b sck5 sck6-a/sck6-b i/o input/output pins for clock signals. i 2 c bus interface scl0, scl1 i/o input/output pins for i 2 c bus interface clocks. bus can be directly driven by the nmos open drain output. sda0, sda1 i/o input/output pins for i 2 c bus interface data. bus can be directly driven by the nmos open drain output. table 1.9 pin functions (4 / 7) classifications pin name i/o description
r01ds0052ej0110 rev.1.10 page 44 of 146 feb 10, 2011 RX62N group, rx62 1 group 1. overview ethernet controller ref50ck input 50-mhz reference clock. this pin inputs reference signals for transmission/reception timings in rmii mode. rmii_crs_dv input indicates that there are carrier detection signals and valid receive data on rmii_rxd1 and rmii_rxd0 in rmii mode. rmii_txd0, rmii_txd1 output 2-bit transmit data in rmii mode. rmii_rxd0, rmii_rxd1 input 2-bit receive data in rmii mode. rmii_txd_en output output pin for data transmit enable signals in rmii mode. rmii_rx_er input indicates an error has occurred during reception of data in rmii mode. et_crs input carrier detecti on/data reception enable pin. et_rx_dv input indicates that there are valid receive data on et_erxd3 to et_erxd0. et_exout output general-purpose external output pin. et_linksta input inputs link status from the phy-lsi. et_etxd0 to et_etxd3 output 4 bits of mii transmit data. et_erxd0 to et_erxd3 input 4 bits of mii receive data. et_tx_en output transmit enable pin. indi cates that transmit data is ready on et_etxd3 to et_etxd0. et_tx_er output transmit error pin. noti fies the phy_lsi of an error during transmission. et_rx_er input receive error pin. re cognizes an error during reception. et_tx_clk input transmit clock pin. this pin inputs reference signals for output timings from et_tx_en, et_etxd3 to et_etxd0, and et_tx_er. et_rx_clk input receive clock pin. this pin inputs reference signals for input timings to et_rx_dv, et_erxd3 to et_erxd0, and et_rx_er. et_col input inputs collision detection signals. et_wol output receives magic packets. et_mdc output outputs reference clock signals for information transfer via et_mdio. et_mdio i/o inputs or outputs bidirectional signals for exchange of management information between the RX62N/rx621 group and the phy-lsi. table 1.9 pin functions (5 / 7) classifications pin name i/o description
r01ds0052ej0110 rev.1.10 page 45 of 146 feb 10, 2011 RX62N group, rx62 1 group 1. overview usb 2.0 host/function module vcc_usb input power-supply pin for the usb. connect this pin to the system power supply even when the usb is not to be used. vss_usb input ground pin for the usb. connect this pin to the system power supply (0 v) even when the usb is not to be used. usb0_dp usb1_dp i/o inputs or outputs d+ data for the usb bus. usb0_dm usb1_dm i/o inputs or outputs d- data for the usb bus. usb0_dprpd usb1_dprpd output enable d+ pull-down. usb0_drpd usb1_drpd output enable d- pull-down. usb0_exicen usb1_exicen output connect these pins to the otg power supply ic. usb0_id usb1_id input connect these pins to the otg power supply ic. usb0_vbusen-a/ usb0_vbusen-b usb1_vbusen-a/ usb1_vbusen-b output vbus power enable pins for the usb. usb0_dpupe-a/ usb0_dpupe-b usb1_dpupe-a/ usb1_dpupe-b output pull-up pins for the usb. usb0_ovrcura/ usb0_ovrcurb usb1_ovrcura/ usb1_ovrcurb input over current pins for the usb. usb0_vbus usb1_vbus input input pins for detection of connection and disconnection of the usb cable. can module crx0 input input pins for the can. ctx0 output output pins for the can. serial peripheral interfaces rspcka-a/ rspcka-b i/o clock input/output pins for the rspi. rspckb-a/ rspckb-b i/o clock input/output pins for the rspi mosia-a/mosia-b mosib-a/mosib-b i/o input or output data output from the master for the rspi. misoa-a/misoa-b misob-a/misob-b i/o input or output data output from the slave for the rspi. ssla0-a/ssla0-b i/o select the slave for the rspi. ssla1-a/ssla1-b ssla2-a/ssla2-b ssla3-a/ssla3-b output sslb0-a/sslb0-b i/o sslb1-a/sslb1-b sslb2-a/sslb2-b sslb3-a/sslb3-b output realtime clock rtcout output ou tput pin for 1-hz clock. a/d converter an0 to an7 input input pins for the analog signals to be processed by the a/d converter. adtrg0#-a/adtrg0#-b adtrg1# input input pins for the external trigger signals that start the a/d conversion. d/a converter da0, da1 output output pins fo r the analog signals from the d/a converter. table 1.9 pin functions (6 / 7) classifications pin name i/o description
r01ds0052ej0110 rev.1.10 page 46 of 146 feb 10, 2011 RX62N group, rx62 1 group 1. overview analog power supply avcc input analog power suppl y pin for the a/d and d/a converters. when the a/d and d/a converters are not in use, connect this pin to the system power supply. avss input ground pin for the a/d and d/a converters. connect this pin to the system power supply (0 v). vrefh input reference power supply pin for the a/d and d/a converters. when the a/d and d/a converters are not in use, connect this pin to the system power supply. vrefl input reference ground pin for the a/d and d/a converters. make sure to connect this pin to the analog reference power supply (0 v). when the a/d and d/a converters are not in use, connect this pin to the system power supply (0 v). for details, see section 34.6.7, ranges of settings for analog power supply and other pins. i/o ports p00 to p03, p05, p07 i/o 6-bit input/output pins. p10 to p17 i/o 8-bit input/output pins. p20 to p27 i/o 8-bit input/output pins. p30 to p34 i/o 5-bit input/output pins. p35 input 1-bit input pin. p40 to p47 i/o 8-bit input/output pins. p50 to p52, p54 to p57 i/o 7-bit input/output pins. p53 input 1-bit input pin. p60 to p67 i/o 8-bit input/output pins. p70 to p77 i/o 8-bit input/output pins. p80 to p85 i/o 6-bit input/output pins. p90 to p97 i/o 8-bit input/output pins. pa0 to pa7 i/o 8-bit input/output pins. pb0 to pb7 i/o 8-bit input/output pins. pc0 to pc7 i/o 8-bit input/output pins. pd0 to pd7 i/o 8-bit input/output pins. pe0 to pe7 i/o 8-bit input/output pins. pf0 to pf4 i/o 5-bit input/output pins. pg0 to pg7 i/o 8-bit input/output pins. table 1.9 pin functions (7 / 7) classifications pin name i/o description
r01ds0052ej0110 rev.1.10 page 47 of 146 feb 10, 2011 RX62N group, rx621 group 2. cpu 2. cpu the rx cpu has sixteen general-purpose registers, nine control registers, and one accumulator used for dsp instructions. figure 2.1 register set of the cpu note: * the stack pointer (sp) can be the interrupt stack pointer (isp) or user stack pointer (usp), according to the value of the u bit in the psw. usp (user stack pointer) isp (interrupt stack pointer) intb (interrupt table register) pc (program counter) psw (processor status word) bpc (backup pc) bpsw (backup psw) fintv (fast interrupt vector register) fpsw (floating-point status word) r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 (sp) * general-purpose register control register b31 b0 b31 b0 dsp instruction register b63 b0 b15b16 acc (accumulator)
r01ds0052ej0110 rev.1.10 page 48 of 146 feb 10, 2011 RX62N group, rx621 group 2. cpu 2.1 general-purpose r egisters (r0 to r15) this cpu has sixteen general-purpose registers (r0 to r15). r1 to r15 can be used as data registers or address registers. r0, a general-purpose register, also functions as the stack pointer (sp). the stack pointer is switched to operate as the interrupt stack pointer (isp) or user stack pointer (usp) by th e value of the stack pointer se lect bit (u) in the processor status word (psw). 2.2 control registers (1) interrupt stack pointer (i sp)/user stack pointer (usp) the stack pointer (sp) can be either of two types, the interrupt stack point er (isp) or the user stack pointer (usp). whether the stack pointer operates as th e isp or usp depends on the value of the stack pointer select bit (u) in the processor status word (psw). set the isp or usp to a multiple of four, as this reduces th e numbers of cycles required to execute interrupt sequences and instructions entai ling stack manipulation. (2) interrupt table register (intb) the interrupt table register (intb) specifies the address where the relocatable vector table starts. set intb to a multiple of four. (3) program counter (pc) the program counter (pc) indicates the a ddress of the instruction being executed. (4) processor status word (psw) the processor status word (psw) indicates results of instruction execution or the state of the cpu. (5) backup pc (bpc) the backup pc (bpc) is provided to speed up response to interrupts. after a fast interrupt has been generated, the conten ts of the program counter (pc) are saved in the bpc. (6) backup psw (bpsw) the backup psw (bpsw) is provided to speed up response to interrupts. after a fast interrupt has been generated, the contents of the processor status word (psw ) are saved in the bpsw. the allocation of bits in the bpsw corresponds to that in the psw. (7) fast interrupt vector register (fintv) the fast interrupt vector register (fintv) is provided to speed up response to interrupts. the fintv register specifies a bran ch destination address when a fa st interrupt has been generated. (8) floating-point status word (fpsw) the floating-point status word (fpsw) indicates the results of floating-point operations. when an exception handling enable bit (e j) enables the exception handling (ej = 1) , the exception cause can be identified by checking the corresponding cj flag in the exception handling routine. if th e exception handling is masked (ej = 0), the occurrence of exception can be ch ecked by reading the fj flag at the end of a series of pro cessing. once the fj flag has been set to 1, this value is retained until it is cleared to 0 by software (j = x, u, z, o, or v).
r01ds0052ej0110 rev.1.10 page 49 of 146 feb 10, 2011 RX62N group, rx621 group 2. cpu (9) accumulator (acc) the accumulator (acc) is a 64-bit register used for dsp instru ctions. the accumulator is also used for the multiply and multiply-and-accumulate instructions; em ul, emulu, fmul, mul, and rmpa, in which case the prior value in the accumulator is modified by execution of the instruction. use the mvtachi and mvtaclo instructions for wr iting to the accumulator. the mvtachi and mvtaclo instructions write data to the higher-order 32 bits (bits 63 to 32) and the lower-order 32 bits (bits 31 to 0), respectively. use the mvfachi and mvfacmi instructions for reading data from th e accumulator. the mvfachi and mvfacmi instructions read data from the higher-order 32 bits (bits 63 to 32) and the middle 32 bits (bits 47 to 16), respectively.
r01ds0052ej0110 rev.1.10 page 50 of 146 feb 10, 2011 RX62N group, rx621 group 3. address space 3. address space 3.1 address space this lsi has a 4-gbyte address space, consisting of the rang e of addresses from 0000 0000 h to ffff ffffh. that is, linear access to an address space of up to 4 gbytes is po ssible, and this contains bo th program and data areas. figure 3.1 shows the memory maps in the re spective operating modes. accessible areas will differ according to the operating mode and states of control bits. figure 3.1 memory map in each operating mode reserved area * 1 reserved area * 1 notes: 1. reserved areas should not be accessed, since the correct operation of lsi is not guaranteed if they are accessed. 2. the address space in boot mode and user boot mode is the same as the address space in single-chip mode. 3. for details on the fcu, see section 37, rom (flash memory for code storage) and section 38, data flash (flash memory for data storage) in the user?s manual: hardware. 0000 0000h 0008 0000h ffff ffffh single-chip mode * 2 on-chip ram reserved area * 1 on-chip rom (program rom) (read only) 0010 0000h peripheral i/o registers 0010 8000h on-chip rom (data flash) 0080 0000h 0100 0000h on-chip rom (program rom) (write only) fff8 0000h fcu-ram * 3 reserved area * 1 peripheral i/o registers reserved area * 1 peripheral i/o registers 007f 8000h 007f a000h 007f c000h 007f c500h 007f fc00h 0001 8000h 0000 0000h 0008 0000h ffff ffffh on-chip rom enabled extended mode on-chip ram reserved area * 1 on-chip rom (program rom) (read only) 0010 0000h peripheral i/o registers 0010 8000h on-chip rom (data flash) 0080 0000h 0100 0000h on-chip rom (program rom) (write only) 0800 0000h fff8 0000h on-chip rom (fcu firmware) * 3 (read only) feff e000h ff00 0000h reserved area * 1 fcu-ram * 3 reserved area * 1 peripheral i/o registers reserved area * 1 peripheral i/o registers 007f 8000h 007f a000h 007f c000h 007f c500h 007f fc00h 0001 8000h reserved area * 1 external address space (cs area) 0000 0000h 0008 0000h ffff ffffh on-chip rom disabled extended mode on-chip ram external address space (cs area) reserved area * 1 0010 0000h peripheral i/o registers 0100 0000h 0800 0000h ff00 0000h reserved area * 1 0001 8000h reserved area * 1 external address space reserved area * 1 reserved area * 1 00f8 0000h 00f8 0000h 1000 0000h on-chip rom (fcu firmware) * 3 (read only) reserved area * 1 feff e000h ff00 0000h 1000 0000h external address space (sdram area) external address space (sdram area) ff7f c000h ff80 c000h reserved area * 1 on-chip rom (user boot) (read only) reserved area * 1 ff7f c000h ff80 c000h reserved area * 1 on-chip rom (user boot) (read only)
r01ds0052ej0110 rev.1.10 page 51 of 146 feb 10, 2011 RX62N group, rx621 group 3. address space 3.2 external address space the external address space is classified into cs areas (cs0 to cs7) and sdram area (sdcs). the cs area is divided into up to 8 areas (cs0 to cs7), each corresponding to the csi# signa l output from a csi# (i = 0 to 7) pin. figure 3.2 shows the address ranges corresponding to the indi vidual cs areas (cs0 to cs 7) and sdram area (sdcs) in on-chip rom disabled extended mode. figure 3.2 correspondence between external address spaces, cs areas (cs0 to cs7), and sdram area (sdcs) (in on-chi p rom disabled extended mode) 0000 0000h 0008 0000h on-chip ram external address space (cs area) reserved area * 1 0010 0000h peripheral i/o registers 0100 0000h 0800 0000h ff00 0000h reserved area * 1 0001 8000h reserved area * 1 external address space * 2 (cs area) 0100 0000h 0200 0000h 0300 0000h 0400 0000h 0500 0000h 0600 0000h 0700 0000h cs7 (16 mbytes) 01ff ffffh 02ff ffffh 03ff ffffh 04ff ffffh 05ff ffffh 06ff ffffh 07ff ffffh cs6 (16 mbytes) cs5 (16 mbytes) cs4 (16 mbytes) cs3 (16 mbytes) cs2 (16 mbytes) cs1 (16 mbytes) ffff ffffh ffff ffffh ff00 0000h cs0 (16 mbytes) notes: 1. reserved areas should not be accessed, since the correct operation of lsi is not guaranteed if they are accessed. 2. the cs0 area is disabled in on-chip rom enabled extended mode. in this mode, the addres s space for addresses above 1000 0000h is as shown in figure 4.1. external address space (sdram area) 1000 0000h 0fff ffffh 0800 0000h sdcs (128 mbytes)
r01ds0052ej0110 rev.1.10 page 52 of 146 feb 10, 2011 RX62N group, rx621 gr oup 4. i/o registers 4. i/o registers table 4.1 list of i/o registers (address order) (1 / 35) address module abbreviation register name register abbreviation number of bits access size number of access cycles 0008 0000h system mode monitor register mdmonr 16 16 3 iclk 0008 0002h system mode status register mdsr 16 16 3 iclk 0008 0006h system system control register 0 syscr0 16 16 3 iclk 0008 0008h system system control register 1 syscr1 16 16 3 iclk 0008 000ch system standby control register sbycr 16 16 3 iclk 0008 0010h system module stop control register a mstpcra 32 32 3 iclk 0008 0014h system module stop control register b mstpcrb 32 32 3 iclk 0008 0018h system module stop control register c mstpcrc 32 32 3 iclk 0008 0020h system system clock control register sckcr 32 32 3 iclk 0008 0030h system external bus clock control register bckcr 8 8 3 iclk 0008 0040h system oscillation stop detection control register ostdcr 16 16 3 iclk 0008 1300h bsc bus error status clear register berclr 8 8 2 iclk 0008 1304h bsc bus error monitoring enable register beren 8 8 2 iclk 0008 1308h bsc bus error status register 1 bersr1 8 8 2 iclk 0008 130ah bsc bus error status register 2 bersr2 16 16 2 iclk 0008 2000h dmac0 dma source address register dmsar 32 32 2 iclk 0008 2004h dmac0 dma destination address register dmdar 32 32 2 iclk 0008 2008h dmac0 dma transfer count register dmcra 32 32 2 iclk 0008 200ch dmac0 dma block transfer count register dmcrb 16 16 2 iclk 0008 2010h dmac0 dma transfer mode register dmtmd 16 16 2 iclk 0008 2013h dmac0 dma interrupt setting register dmint 8 8 2 iclk 0008 2014h dmac0 dma address mode register dmamd 16 16 2 iclk 0008 2018h dmac0 dma offset register dmofr 32 32 2 iclk 0008 201ch dmac0 ma transfer enable register dmcnt 8 8 2 iclk 0008 201dh dmac0 dma software start register dmreq 8 8 2 iclk 0008 201eh dmac0 dma status register dmsts 8 8 2 iclk 0008 201fh dmac0 dma activati on source flag control register dmcsl 8 8 2 iclk 0008 2040h dmac1 dma source address register dmsar 32 32 2 iclk 0008 2044h dmac1 dma destination address register dmdar 32 32 2 iclk 0008 2048h dmac1 dma transfer count register dmcra 32 32 2 iclk 0008 204ch dmac1 dma block transfer count register dmcrb 16 16 2 iclk 0008 2050h dmac1 dma transfer mode register dmtmd 16 16 2 iclk 0008 2053h dmac1 dma interrupt setting register dmint 8 8 2 iclk 0008 2054h dmac1 dma address mode register dmamd 16 16 2 iclk 0008 205ch dmac1 ma transfer enable register dmcnt 8 8 2 iclk 0008 205dh dmac1 dma software start register dmreq 8 8 2 iclk 0008 205eh dmac1 dma status register dmsts 8 8 2 iclk 0008 205fh dmac1 dma activati on source flag control register dmcsl 8 8 2 iclk 0008 2080h dmac2 dma source address register dmsar 32 32 2 iclk 0008 2084h dmac2 dma destination address register dmdar 32 32 2 iclk 0008 2088h dmac2 dma transfer count register dmcra 32 32 2 iclk
r01ds0052ej0110 rev.1.10 page 53 of 146 feb 10, 2011 RX62N group, rx621 gr oup 4. i/o registers 0008 208ch dmac2 dma block transfer count register dmcrb 16 16 2 iclk 0008 2090h dmac2 dma transfer mode register dmtmd 16 16 2 iclk 0008 2093h dmac2 dma interrupt setting register dmint 8 8 2 iclk 0008 2094h dmac2 dma address mode register dmamd 16 16 2 iclk 0008 209ch dmac2 dma transfer enable register dmcnt 8 8 2 iclk 0008 209dh dmac2 dma software start register dmreq 8 8 2 iclk 0008 209eh dmac2 dma status register dmsts 8 8 2 iclk 0008 209fh dmac2 dma activati on source flag control register dmcsl 8 8 2 iclk 0008 20c0h dmac3 dma source address register dmsar 32 32 2 iclk 0008 20c4h dmac3 dma destination address register dmdar 32 32 2 iclk 0008 20c8h dmac3 dma transfer count register dmcra 32 32 2 iclk 0008 20cch dmac3 dma block transfer count register dmcrb 16 16 2 iclk 0008 20d0h dmac3 dma transfer mode register dmtmd 16 16 2 iclk 0008 20d3h dmac3 dma interrupt setting register dmint 8 8 2 iclk 0008 20d4h dmac3 dma address mode register dmamd 16 16 2 iclk 0008 20dch dmac3 dma transfer enable register dmcnt 8 8 2 iclk 0008 20ddh dmac3 dma software start register dmreq 8 8 2 iclk 0008 20deh dmac3 dma status register dmsts 8 8 2 iclk 0008 20dfh dmac3 dma activa tion source flag control register dmcsl 8 8 2 iclk 0008 2200h dmac dmaca start register dmast 8 8 2 iclk 0008 2400h dtc dtc control register dtccr 8 8 2 iclk 0008 2404h dtc dtc vector base register dtcvbr 32 32 2 iclk 0008 2408h dtc dtc address mode register dtcadmod 8 8 2 iclk 0008 240ch dtc dtc module start register dtcst 8 8 2 iclk 0008 240eh dtc dtc status register dtcsts 16 16 2 iclk 0008 2800h exdmac0 exdma source address register edmsar 32 32 1 to 2 bclk* 10 0008 2804h exdmac0 exdma destination address register edmdar 32 32 1 to 2 bclk* 10 0008 2808h exdmac0 exdma transfer count register edmcra 32 32 1 to 2 bclk* 10 0008 280ch exdmac0 exdma block transfer count register edmcrb 16 16 1 to 2 bclk* 10 0008 2810h exdmac0 exdma transfer mode register edmtmd 16 16 1 to 2 bclk* 10 0008 2812h exdmac0 exdma output setting register edmomd 8 8 1 to 2 bclk* 10 0008 2813h exdmac0 exdma interrupt setting register edmint 8 8 1 to 2 bclk* 10 0008 2814h exdmac0 exdma address mode register edmamd 32 32 1 to 2 bclk* 10 0008 2818h exdmac0 exdma output setting register edmofr 32 32 1 to 2 bclk* 10 0008 281ch exdmac0 exdma transfer enable register edmcnt 8 8 1 to 2 bclk* 10 0008 281dh exdmac0 exdma software start register edmreq 8 8 1 to 2 bclk* 10 0008 281eh exdmac0 exdma status register edmsts 8 8 1 to 2 bclk* 10 0008 2820h exdmac0 exdma external request sense mode register edmrmd 8 8 1 to 2 bclk* 10 0008 2821h exdmac0 exdma external request flag register edmerf 8 8 1 to 2 bclk* 10 0008 2822h exdmac0 exdma peripheral request flag register edmprf 8 8 1 to 2 bclk* 10 0008 2840h exdmac1 exdma source address register edmsar 32 32 1 to 2 bclk* 10 0008 2844h exdmac1 exdma destination address register edmdar 32 32 1 to 2 bclk* 10 0008 2848h exdmac1 exdma transfer count register edmcra 32 32 1 to 2 bclk* 10 table 4.1 list of i/o registers (address order) (2 / 35) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0052ej0110 rev.1.10 page 54 of 146 feb 10, 2011 RX62N group, rx621 gr oup 4. i/o registers 0008 284ch exdmac1 exdma block transfer count register edmcrb 16 16 1 to 2 bclk* 10 0008 2850h exdmac1 exdma transfer mode register edmtmd 16 16 1 to 2 bclk* 10 0008 2852h exdmac1 exdma output setting register edmomd 8 8 1 to 2 bclk* 10 0008 2853h exdmac1 exdma interrupt setting register edmint 8 8 1 to 2 bclk* 10 0008 2854h exdmac1 exdma address mode register edmamd 32 32 1 to 2 bclk* 10 0008 285ch exdmac1 exdma transfer enable register edmcnt 8 8 1 to 2 bclk* 10 0008 285dh exdmac1 exdma software start register edmreq 8 8 1 to 2 bclk* 10 0008 285eh exdmac1 exdma status register edmsts 8 8 1 to 2 bclk* 10 0008 2860h exdmac1 exdma external request sense mode register edmrmd 8 8 1 to 2 bclk* 10 0008 2861h exdmac1 exdma external request flag register edmerf 8 8 1 to 2 bclk* 10 0008 2862h exdmac1 exdma peripheral request flag register edmprf 8 8 1 to 2 bclk* 10 0008 2a00h exdmac exdma module start register edmast 8 8 1 to 2 bclk* 10 0008 2be0h exdmac cluster buffer register 0 clsbr0 32 32 1 to 2 bclk* 10 0008 2be4h exdmac cluster buffer register 1 clsbr1 32 32 1 to 2 bclk* 10 0008 2be8h exdmac cluster buffer register 2 clsbr2 32 32 1 to 2 bclk* 10 0008 2bech exdmac cluster buffer register 3 clsbr3 32 32 1 to 2 bclk* 10 0008 2bf0h exdmac cluster buffer register 4 clsbr4 32 32 1 to 2 bclk* 10 0008 2bf4h exdmac cluster buffer register 5 clsbr5 32 32 1 to 2 bclk* 10 0008 2bf8h exdmac cluster buffer register 6 clsbr6 32 32 1 to 2 bclk* 10 0008 3002h bsc cs0 mode register cs0mod 16 16 1 to 2 bclk* 10 0008 3004h bsc cs0 wait control register 1 cs0wcr1 32 32 1 to 2 bclk* 10 0008 3008h bsc cs0 wait control register 2 cs0wcr2 32 32 1 to 2 bclk* 10 0008 3012h bsc cs1 mode register cs1mod 16 16 1 to 2 bclk* 10 0008 3014h bsc cs1 wait control register 1 cs1wcr1 32 32 1 to 2 bclk* 10 0008 3018h bsc cs1 wait control register 2 cs1wcr2 32 32 1 to 2 bclk* 10 0008 3022h bsc cs2 mode register cs2mod 16 16 1 to 2 bclk* 10 0008 3024h bsc cs2 wait control register 1 cs2wcr1 32 32 1 to 2 bclk* 10 0008 3028h bsc cs2 wait control register 2 cs2wcr2 32 32 1 to 2 bclk* 10 0008 3032h bsc cs3 mode register cs3mod 16 16 1 to 2 bclk* 10 0008 3034h bsc cs3 wait control register 1 cs3wcr1 32 32 1 to 2 bclk* 10 0008 3038h bsc cs3 wait control register 2 cs3wcr2 32 32 1 to 2 bclk* 10 0008 3042h bsc cs4 mode register cs4mod 16 16 1 to 2 bclk* 10 0008 3044h bsc cs4 wait control register 1 cs4wcr1 32 32 1 to 2 bclk* 10 0008 3048h bsc cs4 wait control register 2 cs4wcr2 32 32 1 to 2 bclk* 10 0008 3052h bsc cs5 mode register cs5mod 16 16 1 to 2 bclk* 10 0008 3054h bsc cs5 wait control register 1 cs5wcr1 32 32 1 to 2 bclk* 10 0008 3058h bsc cs5 wait control register 2 cs5wcr2 32 32 1 to 2 bclk* 10 0008 3062h bsc cs6 mode register cs6mod 16 16 1 to 2 bclk* 10 0008 3064h bsc cs6 wait control register 1 cs6wcr1 32 32 1 to 2 bclk* 10 0008 3068h bsc cs6 wait control register 2 cs6wcr2 32 32 1 to 2 bclk* 10 0008 3072h bsc cs7 mode register cs7mod 16 16 1 to 2 bclk* 10 0008 3074h bsc cs7 wait control register 1 cs7wcr1 32 32 1 to 2 bclk* 10 0008 3078h bsc cs7 wait control register 2 cs7wcr2 32 32 1 to 2 bclk* 10 0008 3802h bsc cs0 control register cs0cr 16 16 1 to 2 bclk* 10 table 4.1 list of i/o registers (address order) (3 / 35) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0052ej0110 rev.1.10 page 55 of 146 feb 10, 2011 RX62N group, rx621 gr oup 4. i/o registers 0008 380ah bsc cs0 recovery cycle register cs0rec 16 16 1 to 2 bclk* 10 0008 3812h bsc cs1 control register cs1cr 16 16 1 to 2 bclk* 10 0008 381ah bsc cs1 recovery cycle register cs1rec 16 16 1 to 2 bclk* 10 0008 3822h bsc cs2 control register cs2cr 16 16 1 to 2 bclk* 10 0008 382ah bsc cs2 recovery cycle register cs2rec 16 16 1 to 2 bclk* 10 0008 3832h bsc cs3 control register cs3cr 16 16 1 to 2 bclk* 10 0008 383ah bsc cs3 recovery cycle register cs3rec 16 16 1 to 2 bclk* 10 0008 3842h bsc cs4 control register cs4cr 16 16 1 to 2 bclk* 10 0008 384ah bsc cs4 recovery cycle register cs4rec 16 16 1 to 2 bclk* 10 0008 3852h bsc cs5 control register cs5cr 16 16 1 to 2 bclk* 10 0008 385ah bsc cs5 recovery cycle register cs5rec 16 16 1 to 2 bclk* 10 0008 3862h bsc cs6 control register cs6cr 16 16 1 to 2 bclk* 10 0008 386ah bsc cs6 recovery cycle register cs6rec 16 16 1 to 2 bclk* 10 0008 3872h bsc cs7 control register cs7cr 16 16 1 to 2 bclk* 10 0008 387ah bsc cs7 recovery cycle register cs7rec 16 16 1 to 2 bclk* 10 0008 3c00h bsc sdc control register sdccr 8 8 1 to 2 bclk* 10 0008 3c01h bsc sdc mode register sdcmod 8 8 1 to 2 bclk* 10 0008 3c02h bsc sdram access mode register sdamod 8 8 1 to 2 bclk* 10 0008 3c10h bsc sdram self-refresh control register sdself 8 8 1 to 2 bclk* 10 0008 3c14h bsc sdram refresh control register sdrfcr 16 16 1 to 2 bclk* 10 0008 3c16h bsc sdram auto-refresh control register sdrfen 8 8 1 to 2 bclk* 10 0008 3c20h bsc sdram initialization sequence control register sdicr 8 8 1 to 2 bclk* 10 0008 3c24h bsc sdram initialization register sdir 16 16 1 to 2 bclk* 10 0008 3c40h bsc sdram address register sdadr 8 8 1 to 2 bclk* 10 0008 3c44h bsc sdram timing register sdtr 32 32 1 to 2 bclk* 10 0008 3c48h bsc sdram mode register sdmod 16 16 1 to 2 bclk* 10 0008 3c50h bsc sdram status register sdsr 8 8 1 to 2 bclk* 10 0008 7010h icu interrupt request register 016 ir016 8 8 2 iclk 0008 7015h icu interrupt request register 021 ir021 8 8 2 iclk 0008 7017h icu interrupt request register 023 ir023 8 8 2 iclk 0008 701bh icu interrupt request register 027 ir027 8 8 2 iclk 0008 701ch icu interrupt request register 028 ir028 8 8 2 iclk 0008 701dh icu interrupt request register 029 ir029 8 8 2 iclk 0008 701eh icu interrupt request register 030 ir030 8 8 2 iclk 0008 701fh icu interrupt request register 031 ir031 8 8 2 iclk 0008 7020h icu interrupt request register 032 ir032 8 8 2 iclk 0008 7024h icu interrupt request register 036 ir036 8 8 2 iclk 0008 7025h icu interrupt request register 037 ir037 8 8 2 iclk 0008 7026h icu interrupt request register 038 ir038 8 8 2 iclk 0008 7028h icu interrupt request register 040 ir040 8 8 2 iclk 0008 7029h icu interrupt request register 041 ir041 8 8 2 iclk 0008 702ah icu interrupt request register 042 ir042 8 8 2 iclk 0008 702ch icu interrupt request register 044 ir044 8 8 2 iclk 0008 702dh icu interrupt request register 045 ir045 8 8 2 iclk table 4.1 list of i/o registers (address order) (4 / 35) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0052ej0110 rev.1.10 page 56 of 146 feb 10, 2011 RX62N group, rx621 gr oup 4. i/o registers 0008 702eh icu interrupt request register 046 ir046 8 8 2 iclk 0008 702fh icu interrupt request register 047 ir047 8 8 2 iclk 0008 7030h icu interrupt request register 048 ir048 8 8 2 iclk 0008 7031h icu interrupt request register 049 ir049 8 8 2 iclk 0008 7032h icu interrupt request register 050 ir050 8 8 2 iclk 0008 7033h icu interrupt request register 051 ir051 8 8 2 iclk 0008 7038h icu interrupt request register 056 ir056 8 8 2 iclk 0008 7039h icu interrupt request register 057 ir057 8 8 2 iclk 0008 703ah icu interrupt request register 058 ir058 8 8 2 iclk 0008 703bh icu interrupt request register 059 ir059 8 8 2 iclk 0008 703ch icu interrupt request register 060 ir060 8 8 2 iclk 0008 703eh icu interrupt request register 062 ir062 8 8 2 iclk 0008 703fh icu interrupt request register 063 ir063 8 8 2 iclk 0008 7040h icu interrupt request register 064 ir064 8 8 2 iclk 0008 7041h icu interrupt request register 065 ir065 8 8 2 iclk 0008 7042h icu interrupt request register 066 ir066 8 8 2 iclk 0008 7043h icu interrupt request register 067 ir067 8 8 2 iclk 0008 7044h icu interrupt request register 068 ir068 8 8 2 iclk 0008 7045h icu interrupt request register 069 ir069 8 8 2 iclk 0008 7046h icu interrupt request register 070 ir070 8 8 2 iclk 0008 7047h icu interrupt request register 071 ir071 8 8 2 iclk 0008 7048h icu interrupt request register 072 ir072 8 8 2 iclk 0008 7049h icu interrupt request register 073 ir073 8 8 2 iclk 0008 704ah icu interrupt request register 074 ir074 8 8 2 iclk 0008 704bh icu interrupt request register 075 ir075 8 8 2 iclk 0008 704ch icu interrupt request register 076 ir076 8 8 2 iclk 0008 704dh icu interrupt request register 077 ir077 8 8 2 iclk 0008 704eh icu interrupt request register 078 ir078 8 8 2 iclk 0008 704fh icu interrupt request register 079 ir079 8 8 2 iclk 0008 705ah icu interrupt request register 090 ir090 8 8 2 iclk 0008 705bh icu interrupt request register 091 ir091 8 8 2 iclk 0008 705ch icu interrupt request register 092 ir092 8 8 2 iclk 0008 7060h icu interrupt request register 096 ir096 8 8 2 iclk 0008 7062h icu interrupt request register 098 ir098 8 8 2 iclk 0008 7063h icu interrupt request register 099 ir099 8 8 2 iclk 0008 7066h icu interrupt request register 102 ir102 8 8 2 iclk 0008 7072h icu interrupt request register 114 ir114 8 8 2 iclk 0008 7073h icu interrupt request register 115 ir115 8 8 2 iclk 0008 7074h icu interrupt request register 116 ir116 8 8 2 iclk 0008 7075h icu interrupt request register 117 ir117 8 8 2 iclk 0008 7076h icu interrupt request register 118 ir118 8 8 2 iclk 0008 7077h icu interrupt request register 119 ir119 8 8 2 iclk 0008 7078h icu interrupt request register 120 ir120 8 8 2 iclk 0008 7079h icu interrupt request register 121 ir121 8 8 2 iclk 0008 707ah icu interrupt request register 122 ir122 8 8 2 iclk table 4.1 list of i/o registers (address order) (5 / 35) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0052ej0110 rev.1.10 page 57 of 146 feb 10, 2011 RX62N group, rx621 gr oup 4. i/o registers 0008 707bh icu interrupt request register 123 ir123 8 8 2 iclk 0008 707ch icu interrupt request register 124 ir124 8 8 2 iclk 0008 707dh icu interrupt request register 125 ir125 8 8 2 iclk 0008 707eh icu interrupt request register 126 ir126 8 8 2 iclk 0008 707fh icu interrupt request register 127 ir127 8 8 2 iclk 0008 7080h icu interrupt request register 128 ir128 8 8 2 iclk 0008 7081h icu interrupt request register 129 ir129 8 8 2 iclk 0008 7082h icu interrupt request register 130 ir130 8 8 2 iclk 0008 7083h icu interrupt request register 131 ir131 8 8 2 iclk 0008 7084h icu interrupt request register 132 ir132 8 8 2 iclk 0008 7085h icu interrupt request register 133 ir133 8 8 2 iclk 0008 7086h icu interrupt request register 134 ir134 8 8 2 iclk 0008 7087h icu interrupt request register 135 ir135 8 8 2 iclk 0008 7088h icu interrupt request register 136 ir136 8 8 2 iclk 0008 7089h icu interrupt request register 137 ir137 8 8 2 iclk 0008 708ah icu interrupt request register 138 ir138 8 8 2 iclk 0008 708bh icu interrupt request register 139 ir139 8 8 2 iclk 0008 708ch icu interrupt request register 140 ir140 8 8 2 iclk 0008 708dh icu interrupt request register 141 ir141 8 8 2 iclk 0008 708eh icu interrupt request register 142 ir142 8 8 2 iclk 0008 708fh icu interrupt request register 143 ir143 8 8 2 iclk 0008 7090h icu interrupt request register 144 ir144 8 8 2 iclk 0008 7091h icu interrupt request register 145 ir145 8 8 2 iclk 0008 7092h icu interrupt request register 146 ir146 8 8 2 iclk 0008 7093h icu interrupt request register 147 ir147 8 8 2 iclk 0008 7094h icu interrupt request register 148 ir148 8 8 2 iclk 0008 7095h icu interrupt request register 149 ir149 8 8 2 iclk 0008 7096h icu interrupt request register 150 ir150 8 8 2 iclk 0008 7097h icu interrupt request register 151 ir151 8 8 2 iclk 0008 7098h icu interrupt request register 152 ir152 8 8 2 iclk 0008 7099h icu interrupt request register 153 ir153 8 8 2 iclk 0008 709ah icu interrupt request register 154 ir154 8 8 2 iclk 0008 709bh icu interrupt request register 155 ir155 8 8 2 iclk 0008 709ch icu interrupt request register 156 ir156 8 8 2 iclk 0008 709dh icu interrupt request register 157 ir157 8 8 2 iclk 0008 709eh icu interrupt request register 158 ir158 8 8 2 iclk 0008 709fh icu interrupt request register 159 ir159 8 8 2 iclk 0008 70a0h icu interrupt request register 160 ir160 8 8 2 iclk 0008 70a1h icu interrupt request register 161 ir161 8 8 2 iclk 0008 70a2h icu interrupt request register 162 ir162 8 8 2 iclk 0008 70a3h icu interrupt request register 163 ir163 8 8 2 iclk 0008 70a4h icu interrupt request register 164 ir164 8 8 2 iclk 0008 70a5h icu interrupt request register 165 ir165 8 8 2 iclk 0008 70a6h icu interrupt request register 166 ir166 8 8 2 iclk 0008 70a7h icu interrupt request register 167 ir167 8 8 2 iclk table 4.1 list of i/o registers (address order) (6 / 35) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0052ej0110 rev.1.10 page 58 of 146 feb 10, 2011 RX62N group, rx621 gr oup 4. i/o registers 0008 70a8h icu interrupt request register 168 ir168 8 8 2 iclk 0008 70a9h icu interrupt request register 169 ir169 8 8 2 iclk 0008 70aah icu interrupt request register 170 ir170 8 8 2 iclk 0008 70abh icu interrupt request register 171 ir171 8 8 2 iclk 0008 70ach icu interrupt request register 172 ir172 8 8 2 iclk 0008 70adh icu interrupt request register 173 ir173 8 8 2 iclk 0008 70aeh icu interrupt request register 174 ir174 8 8 2 iclk 0008 70afh icu interrupt request register 175 ir175 8 8 2 iclk 0008 70b0h icu interrupt request register 176 ir176 8 8 2 iclk 0008 70b1h icu interrupt request register 177 ir177 8 8 2 iclk 0008 70b2h icu interrupt request register 178 ir178 8 8 2 iclk 0008 70b3h icu interrupt request register 179 ir179 8 8 2 iclk 0008 70b4h icu interrupt request register 180 ir180 8 8 2 iclk 0008 70b5h icu interrupt request register 181 ir181 8 8 2 iclk 0008 70b6h icu interrupt request register 182 ir182 8 8 2 iclk 0008 70b7h icu interrupt request register 183 ir183 8 8 2 iclk 0008 70b8h icu interrupt request register 184 ir184 8 8 2 iclk 0008 70b9h icu interrupt request register 185 ir185 8 8 2 iclk 0008 70c6h icu interrupt request register 198 ir198 8 8 2 iclk 0008 70c7h icu interrupt request register 199 ir199 8 8 2 iclk 0008 70c8h icu interrupt request register 200 ir200 8 8 2 iclk 0008 70c9h icu interrupt request register 201 ir201 8 8 2 iclk 0008 70cah icu interrupt request register 202 ir202 8 8 2 iclk 0008 70cbh icu interrupt request register 203 ir203 8 8 2 iclk 0008 70d6h icu interrupt request register 214 ir214 8 8 2 iclk 0008 70d7h icu interrupt request register 215 ir215 8 8 2 iclk 0008 70d8h icu interrupt request register 216 ir216 8 8 2 iclk 0008 70d9h icu interrupt request register 217 ir217 8 8 2 iclk 0008 70dah icu interrupt request register 218 ir218 8 8 2 iclk 0008 70dbh icu interrupt request register 219 ir219 8 8 2 iclk 0008 70dch icu interrupt request register 220 ir220 8 8 2 iclk 0008 70ddh icu interrupt request register 221 ir221 8 8 2 iclk 0008 70deh icu interrupt request register 222 ir222 8 8 2 iclk 0008 70dfh icu interrupt request register 223 ir223 8 8 2 iclk 0008 70e0h icu interrupt request register 224 ir224 8 8 2 iclk 0008 70e1h icu interrupt request register 225 ir225 8 8 2 iclk 0008 70e2h icu interrupt request register 226 ir226 8 8 2 iclk 0008 70e3h icu interrupt request register 227 ir227 8 8 2 iclk 0008 70e4h icu interrupt request register 228 ir228 8 8 2 iclk 0008 70e5h icu interrupt request register 229 ir229 8 8 2 iclk 0008 70eah icu interrupt request register 234 ir234 8 8 2 iclk 0008 70ebh icu interrupt request register 235 ir235 8 8 2 iclk 0008 70ech icu interrupt request register 236 ir236 8 8 2 iclk 0008 70edh icu interrupt request register 237 ir237 8 8 2 iclk 0008 70eeh icu interrupt request register 238 ir238 8 8 2 iclk table 4.1 list of i/o registers (address order) (7 / 35) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0052ej0110 rev.1.10 page 59 of 146 feb 10, 2011 RX62N group, rx621 gr oup 4. i/o registers 0008 70efh icu interrupt request register 239 ir239 8 8 2 iclk 0008 70f0h icu interrupt request register 240 ir240 8 8 2 iclk 0008 70f1h icu interrupt request register 241 ir241 8 8 2 iclk 0008 70f6h icu interrupt request register 246 ir246 8 8 2 iclk 0008 70f7h icu interrupt request register 247 ir247 8 8 2 iclk 0008 70f8h icu interrupt request register 248 ir248 8 8 2 iclk 0008 70f9h icu interrupt request register 249 ir249 8 8 2 iclk 0008 70fah icu interrupt request register 250 ir250 8 8 2 iclk 0008 70fbh icu interrupt request register 251 ir251 8 8 2 iclk 0008 70fch icu interrupt request register 252 ir252 8 8 2 iclk 0008 70fdh icu interrupt request register 253 ir253 8 8 2 iclk 0008 711bh icu dtc activation enable register 027 dtcer027 8 8 2 iclk 0008 711ch icu dtc activation enable register 028 dtcer028 8 8 2 iclk 0008 711dh icu dtc activation enable register 029 dtcer029 8 8 2 iclk 0008 711eh icu dtc activation enable register 030 dtcer030 8 8 2 iclk 0008 711fh icu dtc activation enable register 031 dtcer031 8 8 2 iclk 0008 7124h icu dtc activation enable register 036 dtcer036 8 8 2 iclk 0008 7125h icu dtc activation enable register 037 dtcer037 8 8 2 iclk 0008 7128h icu dtc activation enable register 040 dtcer040 8 8 2 iclk 0008 7129h icu dtc activation enable register 041 dtcer041 8 8 2 iclk 0008 712dh icu dtc activation enable register 045 dtcer045 8 8 2 iclk 0008 712eh icu dtc activation enable register 046 dtcer046 8 8 2 iclk 0008 7131h icu dtc activation enable register 049 dtcer049 8 8 2 iclk 0008 7132h icu dtc activation enable register 050 dtcer050 8 8 2 iclk 0008 7140h icu dtc activation enable register 064 dtcer064 8 8 2 iclk 0008 7141h icu dtc activation enable register 065 dtcer065 8 8 2 iclk 0008 7142h icu dtc activation enable register 066 dtcer066 8 8 2 iclk 0008 7143h icu dtc activation enable register 067 dtcer067 8 8 2 iclk 0008 7144h icu dtc activation enable register 068 dtcer068 8 8 2 iclk 0008 7145h icu dtc activation enable register 069 dtcer069 8 8 2 iclk 0008 7146h icu dtc activation enable register 070 dtcer070 8 8 2 iclk 0008 7147h icu dtc activation enable register 071 dtcer071 8 8 2 iclk 0008 7148h icu dtc activation enable register 072 dtcer072 8 8 2 iclk 0008 7149h icu dtc activation enable register 073 dtcer073 8 8 2 iclk 0008 714ah icu dtc activation enable register 074 dtcer074 8 8 2 iclk 0008 714bh icu dtc activation enable register 075 dtcer075 8 8 2 iclk 0008 714ch icu dtc activation enable register 076 dtcer076 8 8 2 iclk 0008 714dh icu dtc activation enable register 077 dtcer077 8 8 2 iclk 0008 714eh icu dtc activation enable register 078 dtcer078 8 8 2 iclk 0008 714fh icu dtc activation enable register 079 dtcer079 8 8 2 iclk 0008 7162h icu dtc activation enable register 098 dtcer098 8 8 2 iclk 0008 7163h icu dtc activation enable register 099 dtcer099 8 8 2 iclk 0008 7166h icu dtc activation enable register 102 dtcer102 8 8 2 iclk 0008 7172h icu dtc activation enable register 114 dtcer114 8 8 2 iclk 0008 7173h icu dtc activation enable register 115 dtcer115 8 8 2 iclk table 4.1 list of i/o registers (address order) (8 / 35) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0052ej0110 rev.1.10 page 60 of 146 feb 10, 2011 RX62N group, rx621 gr oup 4. i/o registers 0008 7174h icu dtc activation enable register 116 dtcer116 8 8 2 iclk 0008 7175h icu dtc activation enable register 117 dtcer117 8 8 2 iclk 0008 7179h icu dtc activation enable register 121 dtcer121 8 8 2 iclk 0008 717ah icu dtc activation enable register 122 dtcer122 8 8 2 iclk 0008 717dh icu dtc activation enable register 125 dtcer125 8 8 2 iclk 0008 717eh icu dtc activation enable register 126 dtcer126 8 8 2 iclk 0008 7181h icu dtc activation enable register 129 dtcer129 8 8 2 iclk 0008 7182h icu dtc activation enable register 130 dtcer130 8 8 2 iclk 0008 7183h icu dtc activation enable register 131 dtcer131 8 8 2 iclk 0008 7184h icu dtc activation enable register 132 dtcer132 8 8 2 iclk 0008 7186h icu dtc activation enable register 134 dtcer134 8 8 2 iclk 0008 7187h icu dtc activation enable register 135 dtcer135 8 8 2 iclk 0008 7188h icu dtc activation enable register 136 dtcer136 8 8 2 iclk 0008 7189h icu dtc activation enable register 137 dtcer137 8 8 2 iclk 0008 718ah icu dtc activation enable register 138 dtcer138 8 8 2 iclk 0008 718bh icu dtc activation enable register 139 dtcer139 8 8 2 iclk 0008 718ch icu dtc activation enable register 140 dtcer140 8 8 2 iclk 0008 718dh icu dtc activation enable register 141 dtcer141 8 8 2 iclk 0008 718eh icu dtc activation enable register 142 dtcer142 8 8 2 iclk 0008 718fh icu dtc activation enable register 143 dtcer143 8 8 2 iclk 0008 7190h icu dtc activation enable register 144 dtcer144 8 8 2 iclk 0008 7191h icu dtc activation enable register 145 dtcer145 8 8 2 iclk 0008 7195h icu dtc activation enable register 149 dtcer149 8 8 2 iclk 0008 7196h icu dtc activation enable register 150 dtcer150 8 8 2 iclk 0008 7199h icu dtc activation enable register 153 dtcer153 8 8 2 iclk 0008 719ah icu dtc activation enable register 154 dtcer154 8 8 2 iclk 0008 719dh icu dtc activation enable register 157 dtcer157 8 8 2 iclk 0008 719eh icu dtc activation enable register 158 dtcer158 8 8 2 iclk 0008 719fh icu dtc activation enable register 159 dtcer159 8 8 2 iclk 0008 71a0h icu dtc activation enable register 160 dtcer160 8 8 2 iclk 0008 71a2h icu dtc activation enable register 162 dtcer162 8 8 2 iclk 0008 71a3h icu dtc activation enable register 163 dtcer163 8 8 2 iclk 0008 71a4h icu dtc activation enable register 164 dtcer164 8 8 2 iclk 0008 71a5h icu dtc activation enable register 165 dtcer165 8 8 2 iclk 0008 71a6h icu dtc activation enable register 166 dtcer166 8 8 2 iclk 0008 71a7h icu dtc activation enable register 167 dtcer167 8 8 2 iclk 0008 71a8h icu dtc activation enable register 168 dtcer168 8 8 2 iclk 0008 71a9h icu dtc activation enable register 169 dtcer169 8 8 2 iclk 0008 71aeh icu dtc activation enable register 174 dtcer174 8 8 2 iclk 0008 71afh icu dtc activation enable register 175 dtcer175 8 8 2 iclk 0008 71b1h icu dtc activation enable register 177 dtcer177 8 8 2 iclk 0008 71b2h icu dtc activation enable register 178 dtcer178 8 8 2 iclk 0008 71b4h icu dtc activation enable register 180 dtcer180 8 8 2 iclk 0008 71b5h icu dtc activation enable register 181 dtcer181 8 8 2 iclk 0008 71b7h icu dtc activation enable register 183 dtcer183 8 8 2 iclk table 4.1 list of i/o registers (address order) (9 / 35) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0052ej0110 rev.1.10 page 61 of 146 feb 10, 2011 RX62N group, rx621 gr oup 4. i/o registers 0008 71b8h icu dtc activation enable register 184 dtcer184 8 8 2 iclk 0008 71c6h icu dtc activation enable register 198 dtcer198 8 8 2 iclk 0008 71c7h icu dtc activation enable register 199 dtcer199 8 8 2 iclk 0008 71c8h icu dtc activation enable register 200 dtcer200 8 8 2 iclk 0008 71c9h icu dtc activation enable register 201 dtcer201 8 8 2 iclk 0008 71cah icu dtc activation enable register 202 dtcer202 8 8 2 iclk 0008 71cbh icu dtc activation enable register 203 dtcer203 8 8 2 iclk 0008 71d7h icu dtc activation enable register 215 dtcer215 8 8 2 iclk 0008 71d8h icu dtc activation enable register 216 dtcer216 8 8 2 iclk 0008 71dbh icu dtc activation enable register 219 dtcer219 8 8 2 iclk 0008 71dch icu dtc activation enable register 220 dtcer220 8 8 2 iclk 0008 71dfh icu dtc activation enable register 223 dtcer223 8 8 2 iclk 0008 71e0h icu dtc activation enable register 224 dtcer224 8 8 2 iclk 0008 71e3h icu dtc activation enable register 227 dtcer227 8 8 2 iclk 0008 71e4h icu dtc activation enable register 228 dtcer228 8 8 2 iclk 0008 71ebh icu dtc activation enable register 235 dtcer235 8 8 2 iclk 0008 71ech icu dtc activation enable register 236 dtcer236 8 8 2 iclk 0008 71efh icu dtc activation enable register 239 dtcer239 8 8 2 iclk 0008 71f0h icu dtc activation enable register 240 dtcer240 8 8 2 iclk 0008 71f7h icu dtc activation enable register 247 dtcer247 8 8 2 iclk 0008 71f8h icu dtc activation enable register 248 dtcer248 8 8 2 iclk 0008 71fbh icu dtc activation enable register 251 dtcer251 8 8 2 iclk 0008 71fch icu dtc activation enable register 252 dtcer252 8 8 2 iclk 0008 7202h icu interrupt request enable register 02 ier02 8 8 2 iclk 0008 7203h icu interrupt request enable register 03 ier03 8 8 2 iclk 0008 7204h icu interrupt request enable register 04 ier04 8 8 2 iclk 0008 7205h icu interrupt request enable register 05 ier05 8 8 2 iclk 0008 7206h icu interrupt request enable register 06 ier06 8 8 2 iclk 0008 7207h icu interrupt request enable register 07 ier07 8 8 2 iclk 0008 7208h icu interrupt request enable register 08 ier08 8 8 2 iclk 0008 7209h icu interrupt request enable register 09 ier09 8 8 2 iclk 0008 720bh icu interrupt request enable register 0b ier0b 8 8 2 iclk 0008 720ch icu interrupt request enable register 0c ier0c 8 8 2 iclk 0008 720eh icu interrupt request enable register 0e ier0e 8 8 2 iclk 0008 720fh icu interrupt request enable register 0f ier0f 8 8 2 iclk 0008 7210h icu interrupt request enable register 10 ier10 8 8 2 iclk 0008 7211h icu interrupt request enable register 11 ier11 8 8 2 iclk 0008 7212h icu interrupt request enable register 12 ier12 8 8 2 iclk 0008 7213h icu interrupt request enable register 13 ier13 8 8 2 iclk 0008 7214h icu interrupt request enable register 14 ier14 8 8 2 iclk 0008 7215h icu interrupt request enable register 15 ier15 8 8 2 iclk 0008 7216h icu interrupt request enable register 16 ier16 8 8 2 iclk 0008 7217h icu interrupt request enable register 17 ier17 8 8 2 iclk 0008 7218h icu interrupt request enable register 18 ier18 8 8 2 iclk 0008 7219h icu interrupt request enable register 19 ier19 8 8 2 iclk table 4.1 list of i/o registers (address order) (10 / 35) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0052ej0110 rev.1.10 page 62 of 146 feb 10, 2011 RX62N group, rx621 gr oup 4. i/o registers 0008 721ah icu interrupt request enable register 1a ier1a 8 8 2 iclk 0008 721bh icu interrupt request enable register 1b ier1b 8 8 2 iclk 0008 721ch icu interrupt request enable register 1c ier1c 8 8 2 iclk 0008 721dh icu interrupt request enable register 1d ier1d 8 8 2 iclk 0008 721eh icu interrupt request enable register 1e ier1e 8 8 2 iclk 0008 721fh icu interrupt request enable register 1f ier1f 8 8 2 iclk 0008 72e0h icu software interrupt activation register swintr 8 8 2 iclk 0008 72f0h icu fast interrupt set register fir 16 16 2 iclk 0008 7300h icu interrupt source priority register 00 ipr00 8 8 2 iclk 0008 7301h icu interrupt source priority register 01 ipr01 8 8 2 iclk 0008 7302h icu interrupt source priority register 02 ipr02 8 8 2 iclk 0008 7303h icu interrupt source priority register 03 ipr03 8 8 2 iclk 0008 7304h icu interrupt source priority register 04 ipr04 8 8 2 iclk 0008 7305h icu interrupt source priority register 05 ipr05 8 8 2 iclk 0008 7306h icu interrupt source priority register 06 ipr06 8 8 2 iclk 0008 7307h icu interrupt source priority register 07 ipr07 8 8 2 iclk 0008 7308h icu interrupt source priority register 08 ipr08 8 8 2 iclk 0008 730ch icu interrupt source priority register 0c ipr0c 8 8 2 iclk 0008 730dh icu interrupt source priority register 0d ipr0d 8 8 2 iclk 0008 730eh icu interrupt source priority register 0e ipr0e 8 8 2 iclk 0008 7310h icu interrupt source priority register 10 ipr10 8 8 2 iclk 0008 7311h icu interrupt source priority register 11 ipr11 8 8 2 iclk 0008 7312h icu interrupt source priority register 12 ipr12 8 8 2 iclk 0008 7314h icu interrupt source priority register 14 ipr14 8 8 2 iclk 0008 7315h icu interrupt source priority register 15 ipr15 8 8 2 iclk 0008 7318h icu interrupt source priority register 18 ipr18 8 8 2 iclk 0008 731eh icu interrupt source priority register 1e ipr1e 8 8 2 iclk 0008 731fh icu interrupt source priority register 1f ipr1f 8 8 2 iclk 0008 7320h icu interrupt source priority register 20 ipr20 8 8 2 iclk 0008 7321h icu interrupt source priority register 21 ipr21 8 8 2 iclk 0008 7322h icu interrupt source priority register 22 ipr22 8 8 2 iclk 0008 7323h icu interrupt source priority register 23 ipr23 8 8 2 iclk 0008 7324h icu interrupt source priority register 24 ipr24 8 8 2 iclk 0008 7325h icu interrupt source priority register 25 ipr25 8 8 2 iclk 0008 7326h icu interrupt source priority register 26 ipr26 8 8 2 iclk 0008 7327h icu interrupt source priority register 27 ipr27 8 8 2 iclk 0008 7328h icu interrupt source priority register 28 ipr28 8 8 2 iclk 0008 7329h icu interrupt source priority register 29 ipr29 8 8 2 iclk 0008 732ah icu interrupt source priority register 2a ipr2a 8 8 2 iclk 0008 732bh icu interrupt source priority register 2b ipr2b 8 8 2 iclk 0008 732ch icu interrupt source priority register 2c ipr2c 8 8 2 iclk 0008 732dh icu interrupt source priority register 2d ipr2d 8 8 2 iclk 0008 732eh icu interrupt source priority register 2e ipr2e 8 8 2 iclk 0008 732fh icu interrupt source priority register 2f ipr2f 8 8 2 iclk 0008 733ah icu interrupt source priority register 3a ipr3a 8 8 2 iclk table 4.1 list of i/o registers (address order) (11 / 35) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0052ej0110 rev.1.10 page 63 of 146 feb 10, 2011 RX62N group, rx621 gr oup 4. i/o registers 0008 733bh icu interrupt source priority register 3b ipr3b 8 8 2 iclk 0008 733ch icu interrupt source priority register 3c ipr3c 8 8 2 iclk 0008 7340h icu interrupt source priority register 40 ipr40 8 8 2 iclk 0008 7344h icu interrupt source priority register 44 ipr44 8 8 2 iclk 0008 7345h icu interrupt source priority register 45 ipr45 8 8 2 iclk 0008 7348h icu interrupt source priority register 48 ipr48 8 8 2 iclk 0008 7351h icu interrupt source priority register 51 ipr51 8 8 2 iclk 0008 7352h icu interrupt source priority register 52 ipr52 8 8 2 iclk 0008 7353h icu interrupt source priority register 53 ipr53 8 8 2 iclk 0008 7354h icu interrupt source priority register 54 ipr54 8 8 2 iclk 0008 7355h icu interrupt source priority register 55 ipr55 8 8 2 iclk 0008 7356h icu interrupt source priority register 56 ipr56 8 8 2 iclk 0008 7357h icu interrupt source priority register 57 ipr57 8 8 2 iclk 0008 7358h icu interrupt source priority register 58 ipr58 8 8 2 iclk 0008 7359h icu interrupt source priority register 59 ipr59 8 8 2 iclk 0008 735ah icu interrupt source priority register 5a ipr5a 8 8 2 iclk 0008 735bh icu interrupt source priority register 5b ipr5b 8 8 2 iclk 0008 735ch icu interrupt source priority register 5c ipr5c 8 8 2 iclk 0008 735dh icu interrupt source priority register 5d ipr5d 8 8 2 iclk 0008 735eh icu interrupt source priority register 5e ipr5e 8 8 2 iclk 0008 735fh icu interrupt source priority register 5f ipr5f 8 8 2 iclk 0008 7360h icu interrupt source priority register 60 ipr60 8 8 2 iclk 0008 7361h icu interrupt source priority register 61 ipr61 8 8 2 iclk 0008 7362h icu interrupt source priority register 62 ipr62 8 8 2 iclk 0008 7363h icu interrupt source priority register 63 ipr63 8 8 2 iclk 0008 7364h icu interrupt source priority register 64 ipr64 8 8 2 iclk 0008 7365h icu interrupt source priority register 65 ipr65 8 8 2 iclk 0008 7366h icu interrupt source priority register 66 ipr66 8 8 2 iclk 0008 7367h icu interrupt source priority register 67 ipr67 8 8 2 iclk 0008 7368h icu interrupt source priority register 68 ipr68 8 8 2 iclk 0008 7369h icu interrupt source priority register 69 ipr69 8 8 2 iclk 0008 736ah icu interrupt source priority register 6a ipr6a 8 8 2 iclk 0008 736bh icu interrupt source priority register 6b ipr6b 8 8 2 iclk 0008 7370h icu interrupt source priority register 70 ipr70 8 8 2 iclk 0008 7371h icu interrupt source priority register 71 ipr71 8 8 2 iclk 0008 7372h icu interrupt source priority register 72 ipr72 8 8 2 iclk 0008 7373h icu interrupt source priority register 73 ipr73 8 8 2 iclk 0008 7374h icu interrupt source priority register 74 ipr74 8 8 2 iclk 0008 7375h icu interrupt source priority register 75 ipr75 8 8 2 iclk 0008 7380h icu interrupt source priority register 80 ipr80 8 8 2 iclk 0008 7381h icu interrupt source priority register 81 ipr81 8 8 2 iclk 0008 7382h icu interrupt source priority register 82 ipr82 8 8 2 iclk 0008 7383h icu interrupt source priority register 83 ipr83 8 8 2 iclk 0008 7385h icu interrupt source priority register 85 ipr85 8 8 2 iclk 0008 7386h icu interrupt source priority register 86 ipr86 8 8 2 iclk table 4.1 list of i/o registers (address order) (12 / 35) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0052ej0110 rev.1.10 page 64 of 146 feb 10, 2011 RX62N group, rx621 gr oup 4. i/o registers 0008 7388h icu interrupt source priority register 88 ipr88 8 8 2 iclk 0008 7389h icu interrupt source priority register 89 ipr89 8 8 2 iclk 0008 738ah icu interrupt source priority register 8a ipr8a 8 8 2 iclk 0008 738bh icu interrupt source priority register 8b ipr8b 8 8 2 iclk 0008 738ch icu interrupt source priority register 8c ipr8c 8 8 2 iclk 0008 738dh icu interrupt source priority register 8d ipr8d 8 8 2 iclk 0008 738eh icu interrupt source priority register 8e ipr8e 8 8 2 iclk 0008 738fh icu interrupt source priority register 8f ipr8f 8 8 2 iclk 0008 7400h icu dmaca activation source select register 0 dmrsr0 8 8 2 iclk 0008 7404h icu dmaca activation source select register 1 dmrsr1 8 8 2 iclk 0008 7408h icu dmaca activation source select register 2 dmrsr2 8 8 2 iclk 0008 740ch icu dmaca activation source select register 3 dmrsr3 8 8 2 iclk 0008 7500h icu irq control register 0 irqcr0 8 8 2 iclk 0008 7501h icu irq control register 1 irqcr1 8 8 2 iclk 0008 7502h icu irq control register 2 irqcr2 8 8 2 iclk 0008 7503h icu irq control register 3 irqcr3 8 8 2 iclk 0008 7504h icu irq control register 4 irqcr4 8 8 2 iclk 0008 7505h icu irq control register 5 irqcr5 8 8 2 iclk 0008 7506h icu irq control register 6 irqcr6 8 8 2 iclk 0008 7507h icu irq control register 7 irqcr7 8 8 2 iclk 0008 7508h icu irq control register 8 irqcr8 8 8 2 iclk 0008 7509h icu irq control register 9 irqcr9 8 8 2 iclk 0008 750ah icu irq control register 10 irqcr10 8 8 2 iclk 0008 750bh icu irq control register 11 irqcr11 8 8 2 iclk 0008 750ch icu irq control register 12 irqcr12 8 8 2 iclk 0008 750dh icu irq control register 13 irqcr13 8 8 2 iclk 0008 750eh icu irq control register 14 irqcr14 8 8 2 iclk 0008 750fh icu irq control register 15 irqcr15 8 8 2 iclk 0008 7580h icu non-maskable interrupt status register nmisr 8 8 2 iclk 0008 7581h icu non-maskable interrupt enable register nmier 8 8 2 iclk 0008 7582h icu non-maskable interrupt clear register nmiclr 8 8 2 iclk 0008 7583h icu nmi pin interrupt control register nmicr 8 8 2 iclk 0008 8000h cmt compare match timer start register 0 cmstr0 16 16 2 to 3 pclk* 8 0008 8002h cmt0 compare match timer control register cmcr 16 16 2 to 3 pclk* 8 0008 8004h cmt0 compare match timer counter cmcnt 16 16 2 to 3 pclk* 8 0008 8006h cmt0 compare match timer constant register cmcor 16 16 2 to 3 pclk* 8 0008 8008h cmt1 compare match timer control register cmcr 16 16 2 to 3 pclk* 8 0008 800ah cmt1 compare match timer counter cmcnt 16 16 2 to 3 pclk* 8 0008 800ch cmt1 compare match timer constant register cmcor 16 16 2 to 3 pclk* 8 0008 8010h cmt compare match timer start register 1 cmstr1 16 16 2 to 3 pclk* 8 0008 8012h cmt2 compare match timer control register cmcr 16 16 2 to 3 pclk* 8 0008 8014h cmt2 compare match timer counter cmcnt 16 16 2 to 3 pclk* 8 0008 8016h cmt2 compare match timer constant register cmcor 16 16 2 to 3 pclk* 8 0008 8018h cmt3 compare match timer control register cmcr 16 16 2 to 3 pclk* 8 0008 801ah cmt3 compare match timer counter cmcnt 16 16 2 to 3 pclk* 8 table 4.1 list of i/o registers (address order) (13 / 35) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0052ej0110 rev.1.10 page 65 of 146 feb 10, 2011 RX62N group, rx621 gr oup 4. i/o registers 0008 801ch cmt3 compare match timer constant register cmcor 16 16 2 to 3 pclk* 8 0008 8028h wdt timer control/status register read.tcsr 8 8 2 to 3 pclk* 8 0008 8028h wdt write window a register write.wina 16 16 2 to 3 pclk* 8 0008 8029h wdt timer counter read.tcnt 8 8 2 to 3 pclk* 8 0008 802ah wdt write window b register write.winb 16 16 2 to 3 pclk* 8 0008 802bh wdt reset control/status register read.rstc sr 8 8 2 to 3 pclk* 8 0008 8030h iwdt iwdt refresh register iwdtrr 8 8 2 to 3 pclk* 8 0008 8032h iwdt iwdt control register iwdtcr 16 16 2 to 3 pclk* 8 0008 8034h iwdt iwdt status register iwdtsr 16 16 2 to 3 pclk* 8 0008 8040h ad0 a/d data register a addra 16 16 2 to 3 pclk* 8 0008 8042h ad0 a/d data register b addrb 16 16 2 to 3 pclk* 8 0008 8044h ad0 a/d data register c addrc 16 16 2 to 3 pclk* 8 0008 8046h ad0 a/d data register d addrd 16 16 2 to 3 pclk* 8 0008 8050h ad0 a/d control/status register adcsr 8 8 2 to 3 pclk* 8 0008 8051h ad0 a/d control register adcr 8 8 2 to 3 pclk* 8 0008 8052h ad0 addrn format select register addpr 8 8 2 to 3 pclk* 8 0008 8053h ad0 a/d sampling state register adsstr 8 8 2 to 3 pclk* 8 0008 805fh ad0 a/d self-diagnostic register addiagr 8 8 2 to 3 pclk* 8 0008 8060h ad1 a/d data register a addra 16 16 2 to 3 pclk* 8 0008 8062h ad1 a/d data register b addrb 16 16 2 to 3 pclk* 8 0008 8064h ad1 a/d data register c addrc 16 16 2 to 3 pclk* 8 0008 8066h ad1 a/d data register d addrd 16 16 2 to 3 pclk* 8 0008 8070h ad1 a/d control/status register adcsr 8 8 2 to 3 pclk* 8 0008 8071h ad1 a/d control register adcr 8 8 2 to 3 pclk* 8 0008 8072h ad1 addrn format select register addpr 8 8 2 to 3 pclk* 8 0008 8073h ad1 a/d sampling state register adsstr 8 8 2 to 3 pclk* 8 0008 807fh ad1 a/d self-diagnostic register addiagr 8 8 2 to 3 pclk* 8 0008 80c0h da d/a data register 0 dadr0 16 16 2 to 3 pclk* 8 0008 80c2h da d/a data register 1 dadr1 16 16 2 to 3 pclk* 8 0008 80c4h da d/a control register dacr 8 8 2 to 3 pclk* 8 0008 80c5h da dadrm format select register dadpr 8 8 2 to 3 pclk* 8 0008 81e6h ppg0 ppg output control register pcr 8 8 2 to 3 pclk* 8 0008 81e7h ppg0 ppg output mode register pmr 8 8 2 to 3 pclk* 8 0008 81e8h ppg0 next data enable register h nderh 8 8 2 to 3 pclk* 8 0008 81e9h ppg0 next data enable register l nderl 8 8 2 to 3 pclk* 8 0008 81eah ppg0 output data register h podrh 8 8 2 to 3 pclk* 8 0008 81ebh ppg0 output data register l podrl 8 8 2 to 3 pclk* 8 0008 81ech* 1 ppg0 next data register h ndrh 8 8 2 to 3 pclk* 8 0008 81edh* 2 ppg0 next data register l ndrl 8 8 2 to 3 pclk* 8 0008 81eeh* 1 ppg0 next data register h2 ndrh2 8 8 2 to 3 pclk* 8 0008 81efh* 2 ppg0 next data register l2 ndrl2 8 8 2 to 3 pclk* 8 0008 81f0h ppg1 ppg trigger select register ptrslr 8 8 2 to 3 pclk* 8 0008 81f6h ppg1 ppg output control register pcr 8 8 2 to 3 pclk* 8 0008 81f7h ppg1 ppg output mode register pmr 8 8 2 to 3 pclk* 8 table 4.1 list of i/o registers (address order) (14 / 35) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0052ej0110 rev.1.10 page 66 of 146 feb 10, 2011 RX62N group, rx621 gr oup 4. i/o registers 0008 81f8h ppg1 next data enable register h nderh 8 8 2 to 3 pclk* 8 0008 81f9h ppg1 next data enable register l nderl 8 8 2 to 3 pclk* 8 0008 81fah ppg1 output data register h podrh 8 8 2 to 3 pclk* 8 0008 81fbh ppg1 output data register l podrl 8 8 2 to 3 pclk* 8 0008 81fch* 3 ppg1 next data register h ndrh 8 8 2 to 3 pclk* 8 0008 81fdh* 4 ppg1 next data register l ndrl 8 8 2 to 3 pclk* 8 0008 81feh* 3 ppg1 next data register h2 ndrh2 8 8 2 to 3 pclk* 8 0008 81ffh* 4 ppg1 next data register l2 ndrl2 8 8 2 to 3 pclk* 8 0008 8200h tmr0 timer control register tcr 8 8 2 to 3 pclk* 8 0008 8201h tmr1 timer control register tcr 8 8 2 to 3 pclk* 8 0008 8202h tmr0 timer control/status register tcsr 8 8 2 to 3 pclk* 8 0008 8203h tmr1 timer control/status register tcsr 8 8 2 to 3 pclk* 8 0008 8204h tmr0 time constant register a tcora 8 8 2 to 3 pclk* 8 0008 8205h tmr1 time constant register a tcora 8 8 2 to 3 pclk* 8 0008 8206h tmr0 time constant register b tcorb 8 8 2 to 3 pclk* 8 0008 8207h tmr1 time constant register b tcorb 8 8 2 to 3 pclk* 8 0008 8208h tmr0 timer counter tcnt 8 8 2 to 3 pclk* 8 0008 8209h tmr1 timer counter tcnt 8 8 2 to 3 pclk* 8 0008 820ah tmr0 timer counter control register tccr 8 8 2 to 3 pclk* 8 0008 820bh tmr1 timer counter control register tccr 8 8 2 to 3 pclk* 8 0008 8204h tmr01 time constant register a tcora 16 16 2 to 3 pclk* 8 0008 8206h tmr01 time constant register b tcorb 16 16 2 to 3 pclk* 8 0008 8208h tmr01 timer counter tcnt 16 16 2 to 3 pclk* 8 0008 820ah tmr01 timer counter control register tccr 16 16 2 to 3 pclk* 8 0008 8210h tmr2 timer control register tcr 8 8 2 to 3 pclk* 8 0008 8211h tmr3 timer control register tcr 8 8 2 to 3 pclk* 8 0008 8212h tmr2 timer control/status register tcsr 8 8 2 to 3 pclk* 8 0008 8213h tmr3 timer control/status register tcsr 8 8 2 to 3 pclk* 8 0008 8214h tmr2 time constant register a tcora 8 8 2 to 3 pclk* 8 0008 8215h tmr3 time constant register a tcora 8 8 2 to 3 pclk* 8 0008 8216h tmr2 time constant register b tcorb 8 8 2 to 3 pclk* 8 0008 8217h tmr3 time constant register b tcorb 8 8 2 to 3 pclk* 8 0008 8218h tmr2 timer counter tcnt 8 8 2 to 3 pclk* 8 0008 8219h tmr3 timer counter tcnt 8 8 2 to 3 pclk* 8 0008 821ah tmr2 timer counter control register tccr 8 8 2 to 3 pclk* 8 0008 821bh tmr3 timer counter control register tccr 8 8 2 to 3 pclk* 8 0008 8214h tmr2 time constant register a tcora 16 16 2 to 3 pclk* 8 0008 8216h tmr2 time constant register b tcorb 16 16 2 to 3 pclk* 8 0008 8218h tmr2 timer counter tcnt 16 16 2 to 3 pclk* 8 0008 821ah tmr2 timer counter control register tccr 16 16 2 to 3 pclk* 8 0008 8240h sci0 serial mode register smr 8 8 2 to 3 pclk* 8 0008 8241h sci0 bit rate register brr 8 8 2 to 3 pclk* 8 0008 8242h sci0 serial control register scr 8 8 2 to 3 pclk* 8 0008 8243h sci0 transmit data register tdr 8 8 2 to 3 pclk* 8 0008 8244h sci0 serial status register ssr 8 8 2 to 3 pclk* 8 table 4.1 list of i/o registers (address order) (15 / 35) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0052ej0110 rev.1.10 page 67 of 146 feb 10, 2011 RX62N group, rx621 gr oup 4. i/o registers 0008 8245h sci0 receive data register rdr 8 8 2 to 3 pclk* 8 0008 8246h sci0 smart card mode register scmr 8 8 2 to 3 pclk* 8 0008 8247h sci0 serial extended mode register semr 8 8 2 to 3 pclk* 8 0008 8240h smci0 serial mode register smr 8 8 2 to 3 pclk* 8 0008 8241h smci0 bit rate register brr 8 8 2 to 3 pclk* 8 0008 8242h smci0 serial control register scr 8 8 2 to 3 pclk* 8 0008 8243h smci0 transmit data register tdr 8 8 2 to 3 pclk* 8 0008 8244h smci0 serial status register ssr 8 8 2 to 3 pclk* 8 0008 8245h smci0 receive data register rdr 8 8 2 to 3 pclk* 8 0008 8246h smci0 smart card mode register scmr 8 8 2 to 3 pclk* 8 0008 8248h sci1 serial mode register smr 8 8 2 to 3 pclk* 8 0008 8249h sci1 bit rate register brr 8 8 2 to 3 pclk* 8 0008 824ah sci1 serial control register scr 8 8 2 to 3 pclk* 8 0008 824bh sci1 transmit data register tdr 8 8 2 to 3 pclk* 8 0008 824ch sci1 serial status register ssr 8 8 2 to 3 pclk* 8 0008 824dh sci1 receive data register rdr 8 8 2 to 3 pclk* 8 0008 824eh sci1 smart card mode register scmr 8 8 2 to 3 pclk* 8 0008 824fh sci1 serial extended mode register semr 8 8 2 to 3 pclk* 8 0008 8248h smci1 serial mode register smr 8 8 2 to 3 pclk* 8 0008 8249h smci1 bit rate register brr 8 8 2 to 3 pclk* 8 0008 824ah smci1 serial control register scr 8 8 2 to 3 pclk* 8 0008 824bh smci1 transmit data register tdr 8 8 2 to 3 pclk* 8 0008 824ch smci1 serial status register ssr 8 8 2 to 3 pclk* 8 0008 824dh smci1 receive data register rdr 8 8 2 to 3 pclk* 8 0008 824eh smci1 smart card mode register scmr 8 8 2 to 3 pclk* 8 0008 8250h sci2 serial mode register smr 8 8 2 to 3 pclk* 8 0008 8251h sci2 bit rate register brr 8 8 2 to 3 pclk* 8 0008 8252h sci2 serial control register scr 8 8 2 to 3 pclk* 8 0008 8253h sci2 transmit data register tdr 8 8 2 to 3 pclk* 8 0008 8254h sci2 serial status register ssr 8 8 2 to 3 pclk* 8 0008 8255h sci2 receive data register rdr 8 8 2 to 3 pclk* 8 0008 8256h sci2 smart card mode register scmr 8 8 2 to 3 pclk* 8 0008 8257h sci2 serial extended mode register semr 8 8 2 to 3 pclk* 8 0008 8250h smci2 serial mode register smr 8 8 2 to 3 pclk* 8 0008 8251h smci2 bit rate register brr 8 8 2 to 3 pclk* 8 0008 8252h smci2 serial control register scr 8 8 2 to 3 pclk* 8 0008 8253h smci2 transmit data register tdr 8 8 2 to 3 pclk* 8 0008 8254h smci2 serial status register ssr 8 8 2 to 3 pclk* 8 0008 8255h smci2 receive data register rdr 8 8 2 to 3 pclk* 8 0008 8256h smci2 smart card mode register scmr 8 8 2 to 3 pclk* 8 0008 8258h sci3 serial mode register smr 8 8 2 to 3 pclk* 8 0008 8259h sci3 bit rate register brr 8 8 2 to 3 pclk* 8 0008 825ah sci3 serial control register scr 8 8 2 to 3 pclk* 8 0008 825bh sci3 transmit data register tdr 8 8 2 to 3 pclk* 8 0008 825ch sci3 serial status register ssr 8 8 2 to 3 pclk* 8 table 4.1 list of i/o registers (address order) (16 / 35) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0052ej0110 rev.1.10 page 68 of 146 feb 10, 2011 RX62N group, rx621 gr oup 4. i/o registers 0008 825dh sci3 receive data register rdr 8 8 2 to 3 pclk* 8 0008 825eh sci3 smart card mode register scmr 8 8 2 to 3 pclk* 8 0008 825fh sci3 serial extended mode register semr 8 8 2 to 3 pclk* 8 0008 8258h smci3 serial mode register smr 8 8 2 to 3 pclk* 8 0008 8259h smci3 bit rate register brr 8 8 2 to 3 pclk* 8 0008 825ah smci3 serial control register scr 8 8 2 to 3 pclk* 8 0008 825bh smci3 transmit data register tdr 8 8 2 to 3 pclk* 8 0008 825ch smci3 serial status register ssr 8 8 2 to 3 pclk* 8 0008 825dh smci3 smci3 receive data register rdr 8 8 2 to 3 pclk* 8 0008 825eh smci3 smci3 smart card mode register scmr 8 8 2 to 3 pclk* 8 0008 8268h sci5 serial mode register smr 8 8 2 to 3 pclk* 8 0008 8269h sci5 bit rate register brr 8 8 2 to 3 pclk* 8 0008 826ah sci5 serial control register scr 8 8 2 to 3 pclk* 8 0008 826bh sci5 transmit data register tdr 8 8 2 to 3 pclk* 8 0008 826ch sci5 serial status register ssr 8 8 2 to 3 pclk* 8 0008 826dh sci5 receive data register rdr 8 8 2 to 3 pclk* 8 0008 826eh sci5 smart card mode register scmr 8 8 2 to 3 pclk* 8 0008 826fh sci5 serial extended mode register semr 8 8 2 to 3 pclk* 8 0008 8268h smci5 serial mode register smr 8 8 2 to 3 pclk* 8 0008 8269h smci5 bit rate register brr 8 8 2 to 3 pclk* 8 0008 826ah smci5 serial control register scr 8 8 2 to 3 pclk* 8 0008 826bh smci5 transmit data register tdr 8 8 2 to 3 pclk* 8 0008 826ch smci5 serial status register ssr 8 8 2 to 3 pclk* 8 0008 826dh smci5 receive data register rdr 8 8 2 to 3 pclk* 8 0008 826eh smci5 smart card mode register scmr 8 8 2 to 3 pclk* 8 0008 8270h sci6 serial mode register smr 8 8 2 to 3 pclk* 8 0008 8271h sci6 bit rate register brr 8 8 2 to 3 pclk* 8 0008 8272h sci6 serial control register scr 8 8 2 to 3 pclk* 8 0008 8273h sci6 transmit data register tdr 8 8 2 to 3 pclk* 8 0008 8274h sci6 serial status register ssr 8 8 2 to 3 pclk* 8 0008 8275h sci6 receive data register rdr 8 8 2 to 3 pclk* 8 0008 8276h sci6 smart card mode register scmr 8 8 2 to 3 pclk* 8 0008 8277h sci6 serial extended mode register semr 8 8 2 to 3 pclk* 8 0008 8270h smci6 serial mode register smr 8 8 2 to 3 pclk* 8 0008 8271h smci6 bit rate register brr 8 8 2 to 3 pclk* 8 0008 8272h smci6 serial control register scr 8 8 2 to 3 pclk* 8 0008 8273h smci6 transmit data register tdr 8 8 2 to 3 pclk* 8 0008 8274h smci6 serial status register ssr 8 8 2 to 3 pclk* 8 0008 8275h smci6 receive data register rdr 8 8 2 to 3 pclk* 8 0008 8276h smci6 smart card mode register scmr 8 8 2 to 3 pclk* 8 0008 8280h crc crc control register crccr 8 8 2 to 3 pclk* 8 0008 8281h crc crc data input register crcdir 8 8 2 to 3 pclk* 8 0008 8282h crc crc data output register crcdor 16 16 2 to 3 pclk* 8 0008 8300h riic0 i 2 c bus control register 1 iccr1 8 8 2 to 3 pclk* 8 0008 8301h riic0 i 2 c bus control register 2 iccr2 8 8 2 to 3 pclk* 8 table 4.1 list of i/o registers (address order) (17 / 35) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0052ej0110 rev.1.10 page 69 of 146 feb 10, 2011 RX62N group, rx621 gr oup 4. i/o registers 0008 8302h riic0 i 2 c bus mode register 1 icmr1 8 8 2 to 3 pclk* 8 0008 8303h riic0 i 2 c bus mode register 2 icmr2 8 8 2 to 3 pclk* 8 0008 8304h riic0 i 2 c bus mode register 3 icmr3 8 8 2 to 3 pclk* 8 0008 8305h riic0 i 2 c bus function enable register icfer 8 8 2 to 3 pclk* 8 0008 8306h riic0 i 2 c bus status enable register icser 8 8 2 to 3 pclk* 8 0008 8307h riic0 i 2 c bus interrupt enable register icier 8 8 2 to 3 pclk* 8 0008 8308h riic0 i 2 c bus status register 1 icsr1 8 8 2 to 3 pclk* 8 0008 8309h riic0 i 2 c bus status register 2 icsr2 8 8 2 to 3 pclk* 8 0008 830ah riic0 slave address register l0 sarl0 8 8 2 to 3 pclk* 8 0008 830bh riic0 slave address register u0 saru0 8 8 2 to 3 pclk* 8 0008 830ch riic0 slave address register l1 sarl1 8 8 2 to 3 pclk* 8 0008 830dh riic0 slave address register u1 saru1 8 8 2 to 3 pclk* 8 0008 830eh riic0 slave address register l2 sarl2 8 8 2 to 3 pclk* 8 0008 830fh riic0 slave address register u2 saru2 8 8 2 to 3 pclk* 8 0008 8310h riic0 i 2 c bus bit rate low-level register icbrl 8 8 2 to 3 pclk* 8 0008 8311h riic0 i 2 c bus bit rate high-level register icbrh 8 8 2 to 3 pclk* 8 0008 8312h riic0 i 2 c bus transmit data register icdrt 8 8 2 to 3 pclk* 8 0008 8313h riic0 i 2 c bus receive data register icdrr 8 8 2 to 3 pclk* 8 0008 8320h riic1 i 2 c bus control register 1 iccr1 8 8 2 to 3 pclk* 8 0008 8321h riic1 i 2 c bus control register 2 iccr2 8 8 2 to 3 pclk* 8 0008 8322h riic1 i 2 c bus mode register 1 icmr1 8 8 2 to 3 pclk* 8 0008 8323h riic1 i 2 c bus mode register 2 icmr2 8 8 2 to 3 pclk* 8 0008 8324h riic1 i 2 c bus mode register 3 icmr3 8 8 2 to 3 pclk* 8 0008 8325h riic1 i 2 c bus function enable register icfer 8 8 2 to 3 pclk* 8 0008 8326h riic1 i 2 c bus status enable register icser 8 8 2 to 3 pclk* 8 0008 8327h riic1 i 2 c bus interrupt enable register icier 8 8 2 to 3 pclk* 8 0008 8328h riic1 i 2 c bus status register 1 icsr1 8 8 2 to 3 pclk* 8 0008 8329h riic1 i 2 c bus status register 2 icsr2 8 8 2 to 3 pclk* 8 0008 832ah riic1 slave address register l0 sarl0 8 8 2 to 3 pclk* 8 0008 832bh riic1 slave address register u0 saru0 8 8 2 to 3 pclk* 8 0008 832ch riic1 slave address register l1 sarl1 8 8 2 to 3 pclk* 8 0008 832dh riic1 slave address register u1 saru1 8 8 2 to 3 pclk* 8 0008 832eh riic1 slave address register l2 sarl2 8 8 2 to 3 pclk* 8 0008 832fh riic1 slave address register u2 saru2 8 8 2 to 3 pclk* 8 0008 8330h riic1 i 2 c bus bit rate low-level register icbrl 8 8 2 to 3 pclk* 8 0008 8331h riic1 i 2 c bus bit rate high-level register icbrh 8 8 2 to 3 pclk* 8 0008 8332h riic1 i 2 c bus transmit data register icdrt 8 8 2 to 3 pclk* 8 0008 8333h riic1 i 2 c bus receive data register icdrr 8 8 2 to 3 pclk* 8 0008 8380h rspi0 rspi control register spcr 8 8 2 to 3 pclk* 8 0008 8381h rspi0 rspi slave select polarity register sslp 8 8 2 to 3 pclk* 8 0008 8382h rspi0 rspi pin control register sppcr 8 8 2 to 3 pclk* 8 0008 8383h rspi0 rspi status register spsr 8 8 2 to 3 pclk* 8 0008 8384h rspi0 rspi data register spdr 32 16, 32 2 to 3 pclk* 8 0008 8388h rspi0 rspi sequence control register spscr 8 8 2 to 3 pclk* 8 0008 8389h rspi0 rspi sequence status register spssr 8 8 2 to 3 pclk* 8 table 4.1 list of i/o registers (address order) (18 / 35) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0052ej0110 rev.1.10 page 70 of 146 feb 10, 2011 RX62N group, rx621 gr oup 4. i/o registers 0008 838ah rspi0 rspi bit rate register spbr 8 8 2 to 3 pclk* 8 0008 838bh rspi0 rspi data control register spdcr 8 8 2 to 3 pclk* 8 0008 838ch rspi0 rspi clock delay register spckd 8 8 2 to 3 pclk* 8 0008 838dh rspi0 rspi slave select negation delay register sslnd 8 8 2 to 3 pclk* 8 0008 838eh rspi0 rspi next-access delay register spnd 8 8 2 to 3 pclk* 8 0008 838fh rspi0 rspi control register 2 spcr2 8 8 2 to 3 pclk* 8 0008 8390h rspi0 rspi command register 0 spcmd0 16 16 2 to 3 pclk* 8 0008 8392h rspi0 rspi command register 1 spcmd1 16 16 2 to 3 pclk* 8 0008 8394h rspi0 rspi command register 2 spcmd2 16 16 2 to 3 pclk* 8 0008 8396h rspi0 rspi command register 3 spcmd3 16 16 2 to 3 pclk* 8 0008 8398h rspi0 rspi command register 4 spcmd4 16 16 2 to 3 pclk* 8 0008 839ah rspi0 rspi command register 5 spcmd5 16 16 2 to 3 pclk* 8 0008 839ch rspi0 rspi command register 6 spcmd6 16 16 2 to 3 pclk* 8 0008 839eh rspi0 rspi command register 7 spcmd7 16 16 2 to 3 pclk* 8 0008 83a0h rspi1 rspi control register spcr 8 8 2 to 3 pclk* 8 0008 83a1h rspi1 rspi slave select polarity register sslp 8 8 2 to 3 pclk* 8 0008 83a2h rspi1 rspi pin control register sppcr 8 8 2 to 3 pclk* 8 0008 83a3h rspi1 rspi status register spsr 8 8 2 to 3 pclk* 8 0008 83a4h rspi1 rspi data register spdr 16, 32 16, 32 2 to 3 pclk* 8 0008 83a8h rspi1 rspi sequence control register spscr 8 8 2 to 3 pclk* 8 0008 83a9h rspi1 rspi sequence status register spssr 8 8 2 to 3 pclk* 8 0008 83aah rspi1 rspi bit rate register spbr 8 8 2 to 3 pclk* 8 0008 83abh rspi1 rspi data control register spdcr 8 8 2 to 3 pclk* 8 0008 83ach rspi1 rspi clock delay register spckd 8 8 2 to 3 pclk* 8 0008 83adh rspi1 rspi slave select negation delay register sslnd 8 8 2 to 3 pclk* 8 0008 83aeh rspi1 rspi next-access delay register spnd 8 8 2 to 3 pclk* 8 0008 83afh rspi1 rspi control register 2 spcr2 8 8 2 to 3 pclk* 8 0008 83b0h rspi1 rspi command register 0 spcmd0 16 16 2 to 3 pclk* 8 0008 83b2h rspi1 rspi command register 1 spcmd1 16 16 2 to 3 pclk* 8 0008 83b4h rspi1 rspi command register 2 spcmd2 16 16 2 to 3 pclk* 8 0008 83b6h rspi1 rspi command register 3 spcmd3 16 16 2 to 3 pclk* 8 0008 83b8h rspi1 rspi command register 4 spcmd4 16 16 2 to 3 pclk* 8 0008 83bah rspi1 rspi command register 5 spcmd5 16 16 2 to 3 pclk* 8 0008 83bch rspi1 rspi command register 6 spcmd6 16 16 2 to 3 pclk* 8 0008 83beh rspi1 rspi command register 7 spcmd7 16 16 2 to 3 pclk* 8 0008 8600h mtu3 timer control register tcr 8 8 2 to 3 pclk* 8 0008 8601h mtu4 timer control register tcr 8 8 2 to 3 pclk* 8 0008 8602h mtu3 timer mode register tmdr 8 8 2 to 3 pclk* 8 0008 8603h mtu4 timer mode register tmdr 8 8 2 to 3 pclk* 8 0008 8604h mtu3 timer i/o control register h tiorh 8 8 2 to 3 pclk* 8 0008 8605h mtu3 timer i/o control register l tiorl 8 8 2 to 3 pclk* 8 0008 8606h mtu4 timer i/o control register h tiorh 8 8 2 to 3 pclk* 8 0008 8607h mtu4 timer i/o control register l tiorl 8 8 2 to 3 pclk* 8 0008 8608h mtu3 timer interrupt enable register tier 8 8 2 to 3 pclk* 8 0008 8609h mtu4 timer interrupt enable register tier 8 8 2 to 3 pclk* 8 table 4.1 list of i/o registers (address order) (19 / 35) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0052ej0110 rev.1.10 page 71 of 146 feb 10, 2011 RX62N group, rx621 gr oup 4. i/o registers 0008 860ah mtua timer output master enable register toer 8 8 2 to 3 pclk* 8 0008 860dh mtua timer gate control register tgcr 8 8 2 to 3 pclk* 8 0008 860eh mtua timer output control register 1 tocr1 8 8 2 to 3 pclk* 8 0008 860fh mtua timer output control register 2 tocr2 8 8 2 to 3 pclk* 8 0008 8610h mtu3 timer counter tcnt 16 16 2 to 3 pclk* 8 0008 8612h mtu4 timer counter tcnt 16 16 2 to 3 pclk* 8 0008 8614h mtua timer cycle data register tcdr 16 16 2 to 3 pclk* 8 0008 8616h mtua timer dead time data register tcdr 16 16 2 to 3 pclk* 8 0008 8618h mtu3 timer general register a tgra 16 16 2 to 3 pclk* 8 0008 861ah mtu3 timer general register b tgrb 16 16 2 to 3 pclk* 8 0008 861ch mtu4 timer general register a tgra 16 16 2 to 3 pclk* 8 0008 861eh mtu4 timer general register b tgrb 16 16 2 to 3 pclk* 8 0008 8620h mtua timer subcounter tcnts 16 16 2 to 3 pclk* 8 0008 8622h mtua timer cycle buffer register tcbr 16 16 2 to 3 pclk* 8 0008 8624h mtu3 timer general register c tgrc 16 16 2 to 3 pclk* 8 0008 8626h mtu3 timer general register d tgrd 16 16 2 to 3 pclk* 8 0008 8628h mtu4 timer general register c tgrc 16 16 2 to 3 pclk* 8 0008 862ah mtu4 timer general register d tgrd 16 16 2 to 3 pclk* 8 0008 862ch mtu3 timer status register tsr 8 8 2 to 3 pclk* 8 0008 862dh mtu4 timer status register tsr 8 8 2 to 3 pclk* 8 0008 8630h mtua timer waveform control register titcr 8 8 2 to 3 pclk* 8 0008 8631h mtua timer start register titcnt titcnt 8 8 2 to 3 pclk* 8 0008 8632h mtua timer buffer transfer set register tbter 8 8 2 to 3 pclk* 8 0008 8634h mtua timer dead time enable register tder 8 8 2 to 3 pclk* 8 0008 8636h mtua timer output level buffer register tolbr 8 8 2 to 3 pclk* 8 0008 8638h mtu3 timer buffer operation transfer mode register tbtm 8 8 2 to 3 pclk* 8 0008 8639h mtu4 timer buffer operation transfer mode register tbtm 8 8 2 to 3 pclk* 8 0008 8640h mtu4 timer a/d converter start request control register tadcr 16 16 2 to 3 pclk* 8 0008 8644h mtu4 timer a/d converter start request cycle set register a tadcora 16 16 2 to 3 pclk* 8 0008 8646h mtu4 timer a/d converter start request cycle set register b tadcorb 16 16 2 to 3 pclk* 8 0008 8648h mtu4 timer a/d converter start request cycle set buffer register a tadcobra 16 16 2 to 3 pclk* 8 0008 864ah mtu4 timer a/d converter start request cycle set buffer register b tadcobrb 16 16 2 to 3 pclk* 8 0008 8660h mtua timer waveform control register twcr 8 8 2 to 3 pclk* 8 0008 8680h mtua timer start register tstr 8 8 2 to 3 pclk* 8 0008 8681h mtua timer synchronous register tsyr 8 8 2 to 3 pclk* 8 0008 8684h mtua timer read/write enable register trwer 8 8 2 to 3 pclk* 8 0008 8700h mtu0 timer control register tcr 8 8 2 to 3 pclk* 8 0008 8701h mtu0 timer mode register tmdr 8 8 2 to 3 pclk* 8 0008 8702h mtu0 timer i/o control register h tiorh 8 8 2 to 3 pclk* 8 0008 8703h mtu0 timer i/o control register l tiorl 8 8 2 to 3 pclk* 8 table 4.1 list of i/o registers (address order) (20 / 35) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0052ej0110 rev.1.10 page 72 of 146 feb 10, 2011 RX62N group, rx621 gr oup 4. i/o registers 0008 8704h mtu0 timer interrupt enable register tier 8 8 2 to 3 pclk* 8 0008 8705h mtu0 timer status register tsr 8 8 2 to 3 pclk* 8 0008 8706h mtu0 timer counter tcnt 16 16 2 to 3 pclk* 8 0008 8708h mtu0 timer general register a tgra 16 16 2 to 3 pclk* 8 0008 870ah mtu0 timer general register b tgrb 16 16 2 to 3 pclk* 8 0008 870ch mtu0 timer general register c tgrc 16 16 2 to 3 pclk* 8 0008 870eh mtu0 timer general register d tgrd 16 16 2 to 3 pclk* 8 0008 8720h mtu0 timer general register e tgre 16 16 2 to 3 pclk* 8 0008 8722h mtu0 timer general register f tgrf 16 16 2 to 3 pclk* 8 0008 8724h mtu0 timer interrupt enable register 2 tier2 8 8 2 to 3 pclk* 8 0008 8726h mtu0 timer buffer operation transfer mode register tbtm 8 8 2 to 3 pclk* 8 0008 8780h mtu1 timer control register tcr 8 8 2 to 3 pclk* 8 0008 8781h mtu1 timer mode register tmdr 8 8 2 to 3 pclk* 8 0008 8782h mtu1 timer i/o control register tior 8 8 2 to 3 pclk* 8 0008 8784h mtu1 timer interrupt enable register tier 8 8 2 to 3 pclk* 8 0008 8785h mtu1 timer status register tsr 8 8 2 to 3 pclk* 8 0008 8786h mtu1 timer counter tcnt 16 16 2 to 3 pclk* 8 0008 8788h mtu1 timer general register a tgra 16 16 2 to 3 pclk* 8 0008 878ah mtu1 timer general register b tgrb 16 16 2 to 3 pclk* 8 0008 8790h mtu1 timer input capture control register ticcr 8 8 2 to 3 pclk* 8 0008 8800h mtu2 timer control register tcr 8 8 2 to 3 pclk* 8 0008 8801h mtu2 timer mode register tmdr 8 8 2 to 3 pclk* 8 0008 8802h mtu2 timer i/o control register tior 8 8 2 to 3 pclk* 8 0008 8804h mtu2 timer interrupt enable register tier 8 8 2 to 3 pclk* 8 0008 8805h mtu2 timer status register tsr 8 8 2 to 3 pclk* 8 0008 8806h mtu2 timer counter tcnt 16 16 2 to 3 pclk* 8 0008 8808h mtu2 timer general register a tgra 16 16 2 to 3 pclk* 8 0008 880ah mtu2 timer general register b tgrb 16 16 2 to 3 pclk* 8 0008 8880h mtu5 timer counter u tcntu 16 16 2 to 3 pclk* 8 0008 8882h mtu5 timer general register u tgru 16 16 2 to 3 pclk* 8 0008 8884h mtu5 timer control register u tcru 8 8 2 to 3 pclk* 8 0008 8886h mtu5 timer i/o control register u tioru 8 8 2 to 3 pclk* 8 0008 8890h mtu5 timer counter v tcntv 16 16 2 to 3 pclk* 8 0008 8892h mtu5 timer general register v tgrv 16 16 2 to 3 pclk* 8 0008 8894h mtu5 timer control register v tcrv 8 8 2 to 3 pclk* 8 0008 8896h mtu5 timer i/o control register v tiorv 8 8 2 to 3 pclk* 8 0008 88a0h mtu5 timer counter w tcntw 16 16 2 to 3 pclk* 8 0008 88a2h mtu5 timer general register w tgrw 16 16 2 to 3 pclk* 8 0008 88a4h mtu5 timer control register w tcrw 16 8 2 to 3 pclk* 8 0008 88a6h mtu5 timer i/o control register w tiorw 8 8 2 to 3 pclk* 8 0008 88b2h mtu5 timer interrupt enable register tier 8 8 2 to 3 pclk* 8 0008 88b4h mtu5 timer start register tstr 8 8 2 to 3 pclk* 8 0008 88b6h mtu5 timer compare match clear register tcntcmpcl r 8 8 2 to 3 pclk* 8 table 4.1 list of i/o registers (address order) (21 / 35) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0052ej0110 rev.1.10 page 73 of 146 feb 10, 2011 RX62N group, rx621 gr oup 4. i/o registers 0008 8900h poe input level control/status register 1 icsr1 16 16 2 to 3 pclk* 8 0008 8902h poe output level control/status register 1 ocsr1 16 16 2 to 3 pclk* 8 0008 8904h poe input level control/status register 2 icsr2 16 16 2 to 3 pclk* 8 0008 8906h poe output level control/status register 2 ocsr2 16 16 2 to 3 pclk* 8 0008 8908h poe input level control/status register 3 icsr3 16 16 2 to 3 pclk* 8 0008 890ah poe software port output enable register spoer 8 8 2 to 3 pclk* 8 0008 890bh poe port output enable control register 1 poecr1 8 8 2 to 3 pclk* 8 0008 890ch poe port output enable control register 2 poecr2 16 16 2 to 3 pclk* 8 0008 890eh poe input level control/status register 4 icsr4 16 16 2 to 3 pclk* 8 0008 8a00h mtu9 timer control register tcr 8 8 2 to 3 pclk* 8 0008 8a01h mtu10 timer control register tcr 8 8 2 to 3 pclk* 8 0008 8a02h mtu9 timer mode register tmdr 8 8 2 to 3 pclk* 8 0008 8a03h mtu10 timer mode register tmdr 8 8 2 to 3 pclk* 8 0008 8a04h mtu9 timer i/o control register h tiorh 8 8 2 to 3 pclk* 8 0008 8a05h mtu9 timer i/o control register l tiorl 8 8 2 to 3 pclk* 8 0008 8a06h mtu10 timer i/o control register h tiorh 8 8 2 to 3 pclk* 8 0008 8a07h mtu10 timer i/o control register l tiorl 8 8 2 to 3 pclk* 8 0008 8a08h mtu9 timer interrupt enable register tier 8 8 2 to 3 pclk* 8 0008 8a09h mtu10 timer interrupt enable register tier 8 8 2 to 3 pclk* 8 0008 8a0ah mtub timer output master enable register toer 8 8 2 to 3 pclk* 8 0008 8a0dh mtub timer gate control register tgcr 8 8 2 to 3 pclk* 8 0008 8a0eh mtub timer output control register 1 tocr1 8 8 2 to 3 pclk* 8 0008 8a0fh mtub timer output control register 2 tocr2 8 8 2 to 3 pclk* 8 0008 8a10h mtu9 timer counter tcnt 16 16 2 to 3 pclk* 8 0008 8a12h mtu10 timer counter tcnt 16 16 2 to 3 pclk* 8 0008 8a14h mtub timer cycle data register tcdr 16 16 2 to 3 pclk* 8 0008 8a16h mtub timer dead time data register tddr 16 16 2 to 3 pclk* 8 0008 8a18h mtu9 timer general register a tgra 16 16 2 to 3 pclk* 8 0008 8a1ah mtu9 timer general register b tgrb 16 16 2 to 3 pclk* 8 0008 8a1ch mtu10 timer general register a tgra 16 16 2 to 3 pclk* 8 0008 8a1eh mtu10 timer general register b tgrb 16 16 2 to 3 pclk* 8 0008 8a20h mtub timer subcounter tcnts 16 16 2 to 3 pclk* 8 0008 8a22h mtub mtub timer cycle buffer register tcbr 16 16 2 to 3 pclk* 8 0008 8a24h mtu9 timer general register c tgrc 16 16 2 to 3 pclk* 8 0008 8a26h mtu9 timer general register d tgrd 16 16 2 to 3 pclk* 8 0008 8a28h mtu10 timer general register c tgrc 16 16 2 to 3 pclk* 8 0008 8a2ah mtu10 timer general register d tgrd 16 16 2 to 3 pclk* 8 0008 8a2ch mtu9 timer status register tsr 8 8 2 to 3 pclk* 8 0008 8a2dh mtu10 timer status register tsr 8 8 2 to 3 pclk* 8 0008 8a30h mtub timer interrupt skipping set register titcr 8 8 2 to 3 pclk* 8 0008 8a31h mtub timer interrupt skipping counter titcnt 8 8 2 to 3 pclk* 8 0008 8a32h mtub tub timer dead time enable register tbter 8 8 2 to 3 pclk* 8 0008 8a34h mtub timer dead time enable register tder 8 8 2 to 3 pclk* 8 0008 8a36h mtub timer output level buffer register tolbr 8 8 2 to 3 pclk* 8 table 4.1 list of i/o registers (address order) (22 / 35) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0052ej0110 rev.1.10 page 74 of 146 feb 10, 2011 RX62N group, rx621 gr oup 4. i/o registers 0008 8a38h mtu9 timer buffer operation transfer mode register tbtm 8 8 2 to 3 pclk* 8 0008 8a39h mtu10 timer buffer operation transfer mode register tbtm 8 8 2 to 3 pclk* 8 0008 8a40h mtu10 timer a/d converter start request control register tadcr 16 16 2 to 3 pclk* 8 0008 8a44h mtu10 timer a/d converter start request cycle set register a tadcora 16 16 2 to 3 pclk* 8 0008 8a46h mtu10 timer a/d converter start request cycle set register b tadcorb 16 16 2 to 3 pclk* 8 0008 8a48h mtu10 timer a/d converter start request cycle set buffer register a tadcobra 16 16 2 to 3 pclk* 8 0008 8a4ah mtu10 timer a/d converter start request cycle set buffer register b tadcobrb 16 16 2 to 3 pclk* 8 0008 8a60h mtub timer waveform control register twcr 8 8 2 to 3 pclk* 8 0008 8a80h mtub timer start register tstr 8 8 2 to 3 pclk* 8 0008 8a81h mtub mtub timer synchronous register tsyr 8 8 2 to 3 pclk* 8 0008 8a84h mtub mtub timer read/write enable register trwer 8 8 2 to 3 pclk* 8 0008 8b00h mtu6 timer control register tcr 8 8 2 to 3 pclk* 8 0008 8b01h mtu6 timer mode register tmdr 8 8 2 to 3 pclk* 8 0008 8b02h mtu6 timer i/o control register h tiorh 8 8 2 to 3 pclk* 8 0008 8b03h mtu6 timer i/o control register l tiorl 8 8 2 to 3 pclk* 8 0008 8b04h mtu6 timer interrupt enable register tier 8 8 2 to 3 pclk* 8 0008 8b05h mtu6 timer status register tsr 8 8 2 to 3 pclk* 8 0008 8b06h mtu6 timer counter tcnt 16 16 2 to 3 pclk* 8 0008 8b08h mtu6 timer general register a tgra 16 16 2 to 3 pclk* 8 0008 8b0ah mtu6 timer general register b tgrb 16 16 2 to 3 pclk* 8 0008 8b0ch mtu6 timer general register c tgrc 16 16 2 to 3 pclk* 8 0008 8b0eh mtu6 timer general register d tgrd 16 16 2 to 3 pclk* 8 0008 8b20h mtu6 timer general register e tgre 16 16 2 to 3 pclk* 8 0008 8b22h mtu6 timer general register f tgrf 16 16 2 to 3 pclk* 8 0008 8b24h mtu6 timer interrupt enable register 2 tier2 8 8 2 to 3 pclk* 8 0008 8b26h mtu6 timer buffer operation transfer mode register tbtm 8 8 2 to 3 pclk* 8 0008 8b80h mtu7 timer control register tcr 8 8 2 to 3 pclk* 8 0008 8b81h mtu7 timer mode register tmdr 8 8 2 to 3 pclk* 8 0008 8b82h mtu7 timer i/o control register tior 8 8 2 to 3 pclk* 8 0008 8b84h mtu7 timer interrupt enable register tier 8 8 2 to 3 pclk* 8 0008 8b85h mtu7 timer status register tsr 8 8 2 to 3 pclk* 8 0008 8b86h mtu7 timer counter tcnt 16 16 2 to 3 pclk* 8 0008 8b88h mtu7 timer general register a tgra 16 16 2 to 3 pclk* 8 0008 8b8ah mtu7 timer general register b tgrb 16 16 2 to 3 pclk* 8 0008 8b90h mtu7 timer input capture control register ticcr 8 8 2 to 3 pclk* 8 0008 8c00h mtu8 timer control register tcr 8 8 2 to 3 pclk* 8 0008 8c01h mtu8 timer mode register tmdr 8 8 2 to 3 pclk* 8 0008 8c02h mtu8 timer i/o control register tior 8 8 2 to 3 pclk* 8 0008 8c04h mtu8 timer interrupt enable register tier 8 8 2 to 3 pclk* 8 table 4.1 list of i/o registers (address order) (23 / 35) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0052ej0110 rev.1.10 page 75 of 146 feb 10, 2011 RX62N group, rx621 gr oup 4. i/o registers 0008 8c05h mtu8 timer status register tsr 8 8 2 to 3 pclk* 8 0008 8c06h mtu8 timer counter tcnt 16 16 2 to 3 pclk* 8 0008 8c08h mtu8 timer general register a tgra 16 16 2 to 3 pclk* 8 0008 8c0ah mtu8 timer general register b tgrb 16 16 2 to 3 pclk* 8 0008 8c80h mtu11 timer counter u tcntu 16 16 2 to 3 pclk* 8 0008 8c82h mtu11 timer general register u tgru 16 16 2 to 3 pclk* 8 0008 8c84h mtu11 timer control register u tcru 8 8 2 to 3 pclk* 8 0008 8c86h mtu11 timer i/o control register u tioru 8 8 2 to 3 pclk* 8 0008 8c90h mtu11 timer counter v tcntv 16 16 2 to 3 pclk* 8 0008 8c92h mtu11 timer general register v tgrv 16 16 2 to 3 pclk* 8 0008 8c94h mtu11 timer control register v tcrv 8 8 2 to 3 pclk* 8 0008 8c96h mtu11 timer i/o control register v tiorv 8 8 2 to 3 pclk* 8 0008 8ca0h mtu11 timer counter w tcntw 16 16 2 to 3 pclk* 8 0008 8ca2h mtu11 timer general register w tgrw 16 16 2 to 3 pclk* 8 0008 8ca4h mtu11 timer control register w tcrw 8 8 2 to 3 pclk* 8 0008 8ca6h mtu11 timer i/o control register w tiorw 8 8 2 to 3 pclk* 8 0008 8cb2h mtu11 timer interrupt enable register tier 8 8 2 to 3 pclk* 8 0008 8cb4h mtu11 timer start register tstr 8 8 2 to 3 pclk* 8 0008 8cb6h mtu11 timer compare match clear register tcntcmpclr 8 8 2 to 3 pclk* 8 0008 9000h s12ad a/d control register adcsr 8 8 2 to 3 pclk* 8 0008 9004h s12ad a/d channel select register adans 16 16 2 to 3 pclk* 8 0008 9008h s12ad a/d-converted value addition mode select register adads 16 16 2 to 3 pclk* 8 0008 900ch s12ad a/d-converted value addition count select register adadc 8 8 2 to 3 pclk* 8 0008 900eh s12ad a/d control extended register adcer 16 16 2 to 3 pclk* 8 0008 9010h s12ad a/d start trigger select register adstrgr 8 8 2 to 3 pclk* 8 0008 9020h s12ad a/d data register 0 addr0 16 16 2 to 3 pclk* 8 0008 9022h s12ad a/d data register 1 addr1 16 16 2 to 3 pclk* 8 0008 9024h s12ad a/d data register 2 addr2 16 16 2 to 3 pclk* 8 0008 9026h s12ad a/d data register 3 addr3 16 16 2 to 3 pclk* 8 0008 9028h s12ad a/d data register 4 addr4 16 16 2 to 3 pclk* 8 0008 902ah s12ad a/d data register 5 addr5 16 16 2 to 3 pclk* 8 0008 902ch s12ad a/d data register 6 addr6 16 16 2 to 3 pclk* 8 0008 902eh s12ad a/d data register 7 addr7 16 16 2 to 3 pclk* 8 0008 c000h port0 data direction register ddr 8 8 2 to 3 pclk* 8 0008 c001h port1 data direction register ddr 8 8 2 to 3 pclk* 8 0008 c002h port2 data direction register ddr 8 8 2 to 3 pclk* 8 0008 c003h port3 data direction register ddr 8 8 2 to 3 pclk* 8 0008 c004h port4 data direction register ddr 8 8 2 to 3 pclk* 8 0008 c005h port5 data direction register ddr 8 8 2 to 3 pclk* 8 0008 c006h port6 data direction register ddr * 6 * 7 8 8 2 to 3 pclk* 8 0008 c007h port7 data direction register ddr * 6 * 7 8 8 2 to 3 pclk* 8 0008 c008h port8 data direction register ddr * 6 * 7 8 8 2 to 3 pclk* 8 0008 c009h port9 data direction register ddr * 6 * 7 8 8 2 to 3 pclk* 8 table 4.1 list of i/o registers (address order) (24 / 35) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0052ej0110 rev.1.10 page 76 of 146 feb 10, 2011 RX62N group, rx621 gr oup 4. i/o registers 0008 c00ah porta data direction register ddr 8 8 2 to 3 pclk* 8 0008 c00bh portb data direction register ddr 8 8 2 to 3 pclk* 8 0008 c00ch portc data direction register ddr 8 8 2 to 3 pclk* 8 0008 c00dh portd data direction register ddr 8 8 2 to 3 pclk* 8 0008 c00eh porte data direction register ddr * 7 8 8 2 to 3 pclk* 8 0008 c00fh portf data direction register ddr * 5 * 6 * 7 8 8 2 to 3 pclk* 8 0008 c010h portg data direction register ddr * 5 * 6 * 7 8 8 2 to 3 pclk* 8 0008 c020h port0 data register dr 8 8 2 to 3 pclk* 8 0008 c021h port1 data register dr 8 8 2 to 3 pclk* 8 0008 c022h port2 data register dr 8 8 2 to 3 pclk* 8 0008 c023h port3 data register dr 8 8 2 to 3 pclk* 8 0008 c024h port4 data register dr 8 8 2 to 3 pclk* 8 0008 c025h port5 data register dr 8 8 2 to 3 pclk* 8 0008 c026h port6 data register dr * 6 * 7 8 8 2 to 3 pclk* 8 0008 c027h port7 data register dr * 6 * 7 8 8 2 to 3 pclk* 8 0008 c028h port8 data register dr * 6 * 7 8 8 2 to 3 pclk* 8 0008 c029h port9 data register dr * 6 * 7 8 8 2 to 3 pclk* 8 0008 c02ah porta data register dr 8 8 2 to 3 pclk* 8 0008 c02bh portb data register dr 8 8 2 to 3 pclk* 8 0008 c02ch portc data register dr 8 8 2 to 3 pclk* 8 0008 c02dh portd data register dr 8 8 2 to 3 pclk* 8 0008 c02eh porte data register dr * 7 8 8 2 to 3 pclk* 8 0008 c02fh portf data register dr * 5 * 6 * 7 8 8 2 to 3 pclk* 8 0008 c030h portg data register dr ** 5 * 6 * 7 8 8 2 to 3 pclk* 8 0008 c040h port0 port register port 8 8 2 to 3 pclk* 8 0008 c041h port1 port register port 8 8 2 to 3 pclk* 8 0008 c042h port2 port register port 8 8 2 to 3 pclk* 8 0008 c043h port3 port register port 8 8 2 to 3 pclk* 8 0008 c044h port4 port register port 8 8 2 to 3 pclk* 8 0008 c045h port5 port register port 8 8 2 to 3 pclk* 8 0008 c046h port6 port register port * 6 * 7 8 8 2 to 3 pclk* 8 0008 c047h port7 port register port * 6 * 7 8 8 2 to 3 pclk* 8 0008 c048h port8 port register port * 6 * 7 8 8 2 to 3 pclk* 8 0008 c049h port9 port register port * 6 * 7 8 8 2 to 3 pclk* 8 0008 c04ah porta port register port 8 8 2 to 3 pclk* 8 0008 c04bh portb port register port 8 8 2 to 3 pclk* 8 0008 c04ch portc port register port 8 8 2 to 3 pclk* 8 0008 c04dh portd port register port 8 8 2 to 3 pclk* 8 0008 c04eh porte port register port * 7 8 8 2 to 3 pclk* 8 0008 c04fh portf port register port * 5 * 6 * 7 8 8 2 to 3 pclk* 8 0008 c050h portg port register port * 5 * 6 * 7 8 8 2 to 3 pclk* 8 0008 c060h port0 input buffer control register icr 8 8 2 to 3 pclk* 8 0008 c061h port1 input buffer control register icr 8 8 2 to 3 pclk* 8 0008 c062h port2 input buffer control register icr 8 8 2 to 3 pclk* 8 0008 c063h port3 input buffer control register icr 8 8 2 to 3 pclk* 8 table 4.1 list of i/o registers (address order) (25 / 35) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0052ej0110 rev.1.10 page 77 of 146 feb 10, 2011 RX62N group, rx621 gr oup 4. i/o registers 0008 c064h port4 input buffer control register icr 8 8 2 to 3 pclk* 8 0008 c065h port5 input buffer control register icr 8 8 2 to 3 pclk* 8 0008 c066h port6 input buffer control register icr * 6 * 7 8 8 2 to 3 pclk* 8 0008 c067h port7 input buffer control register icr * 6 * 7 8 8 2 to 3 pclk* 8 0008 c068h port8 input buffer control register icr * 6 * 7 8 8 2 to 3 pclk* 8 0008 c069h port9 input buffer control register icr * 6 * 7 8 8 2 to 3 pclk* 8 0008 c06ah porta input buffer control register icr 8 8 2 to 3 pclk* 8 0008 c06bh portb input buffer control register icr 8 8 2 to 3 pclk* 8 0008 c06ch portc input buffer control register icr 8 8 2 to 3 pclk* 8 0008 c06dh portd input buffer control register icr 8 8 2 to 3 pclk* 8 0008 c06eh porte input buffer control register icr * 7 8 8 2 to 3 pclk* 8 0008 c06fh portf input buffer control register icr * 5 * 6 * 7 8 8 2 to 3 pclk* 8 0008 c070h portg input buffer control register icr * 5 * 6 * 7 8 8 2 to 3 pclk* 8 0008 c080h port0 open drain control register odr 8 8 2 to 3 pclk* 8 0008 c081h port1 open drain control register odr 8 8 2 to 3 pclk* 8 0008 c082h port2 open drain control register odr 8 8 2 to 3 pclk* 8 0008 c083h port3 open drain control register odr 8 8 2 to 3 pclk* 8 0008 c08ch portc open drain control register odr 8 8 2 to 3 pclk* 8 0008 c0c9h port9 pull-up resistor control register pcr * 6 * 7 8 8 2 to 3 pclk* 8 0008 c0cah porta pull-up resistor control register pcr 8 8 2 to 3 pclk* 8 0008 c0cbh portb pull-up resistor control register pcr 8 8 2 to 3 pclk* 8 0008 c0cch portc pull-up resistor control register pcr 8 8 2 to 3 pclk* 8 0008 c0cdh portd pull-up resistor control register pcr 8 8 2 to 3 pclk* 8 0008 c0ceh porte pull-up resistor control register pcr * 7 8 8 2 to 3 pclk* 8 0008 c0d0h portg pull-up resistor control register pcr * 5 * 6 * 7 8 8 2 to 3 pclk* 8 0008 c100h ioport port function register 0 pf0cse 8 8 2 to 3 pclk* 8 0008 c101h ioport port function register 1 pf1css * 6 * 7 8 8 2 to 3 pclk* 8 0008 c102h ioport port function register 2 pf2css * 6 * 7 8 8 2 to 3 pclk* 8 0008 c103h ioport port function register 3 pf3bus 8 8 2 to 3 pclk* 8 0008 c104h ioport port function register 4 pf4bus 8 8 2 to 3 pclk* 8 0008 c105h ioport port function register 5 pf5bus 8 8 2 to 3 pclk* 8 0008 c106h ioport port function register 6 pf6bus 8 8 2 to 3 pclk* 8 0008 c107h ioport port function register 7 pf7dma 8 8 2 to 3 pclk* 8 0008 c108h ioport port function register 8 pf8irq 8 8 2 to 3 pclk* 8 0008 c109h ioport port function register 9 pf9irq 8 8 2 to 3 pclk* 8 0008 c10ah ioport port function register a pfaadc 8 8 2 to 3 pclk* 8 0008 c10bh ioport port function register b pfbtmr 8 8 2 to 3 pclk* 8 0008 c10ch ioport port function register c pfcmtu 8 8 2 to 3 pclk* 8 0008 c10dh ioport port function register d pfdmtu 8 8 2 to 3 pclk* 8 0008 c10eh ioport port function register e pfenet 8 8 2 to 3 pclk* 8 0008 c10fh ioport port function register f pffsci 8 8 2 to 3 pclk* 8 0008 c110h ioport port function register g pfgspi 8 8 2 to 3 pclk* 8 0008 c111h ioport port function register h pfhspi 8 8 2 to 3 pclk* 8 0008 c113h ioport port function register j pfjcan 8 8 2 to 3 pclk* 8 0008 c114h ioport port function register k pfkusb 8 8 2 to 3 pclk* 8 table 4.1 list of i/o registers (address order) (26 / 35) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0052ej0110 rev.1.10 page 78 of 146 feb 10, 2011 RX62N group, rx621 gr oup 4. i/o registers 0008 c115h ioport port function register l pflusb * 6 * 7 8 8 2 to 3 pclk* 8 0008 c116h ioport port function register m pfmpoe * 7 8 8 2 to 3 pclk* 8 0008 c117h ioport port function register n pfnpoe * 7 8 8 2 to 3 pclk* 8 0008 c280h system deep standby control register dpsbycr 8 8 4 to 5 pclk* 8 0008 c281h system deep standby wait control register dpswcr 8 8 4 to 5 pclk* 8 0008 c282h system deep standby interrupt enable register dpsier 8 8 4 to 5 pclk* 8 0008 c283h system deep standby interrupt flag register dpsifr 8 8 4 to 5 pclk* 8 0008 c284h system deep standby interrupt edge register dpsiegr 8 8 4 to 5 pclk* 8 0008 c285h system reset status register rstsr 8 8 4 to 5 pclk* 8 0008 c289h flash flash write erase protection register fwepror 8 8 4 to 5 pclk* 8 0008 c28ah system sub-clock oscillator c ontrol register subosccr 8 8 4 to 5 pclk* 8 0008 c28c system key code register for voltage detection control register lvdkeyr 8 8 4 to 5 pclk* 8 0008 c28dh system voltage detection control register lvdcr 8 8 4 to 5 pclk* 8 0008 c290h system deep standby backup regi ster 0 dpsbkr0 8 8 4 to 5 pclk* 8 0008 c291h system deep standby backup regi ster 1 dpsbkr1 8 8 4 to 5 pclk* 8 0008 c292h system deep standby backup regi ster 2 dpsbkr2 8 8 4 to 5 pclk* 8 0008 c293h system deep standby backup regi ster 3 dpsbkr3 8 8 4 to 5 pclk* 8 0008 c294h system deep standby backup regi ster 4 dpsbkr4 8 8 4 to 5 pclk* 8 0008 c295h system deep standby backup regi ster 5 dpsbkr5 8 8 4 to 5 pclk* 8 0008 c296h system deep standby backup regi ster 6 dpsbkr6 8 8 4 to 5 pclk* 8 0008 c297h system deep standby backup regi ster 7 dpsbkr7 8 8 4 to 5 pclk* 8 0008 c298h system deep standby backup regi ster 8 dpsbkr8 8 8 4 to 5 pclk* 8 0008 c299h system deep standby backup regi ster 9 dpsbkr9 8 8 4 to 5 pclk* 8 0008 c29ah system deep standby backup regi ster 10 dpsbkr10 8 8 4 to 5 pclk* 8 0008 c29bh system deep standby backup regi ster 11 dpsbkr11 8 8 4 to 5 pclk* 8 0008 c29ch system deep standby backup regi ster 12 dpsbkr12 8 8 4 to 5 pclk* 8 0008 c29dh system deep standby backup regi ster 13 dpsbkr13 8 8 4 to 5 pclk* 8 0008 c29eh system deep standby backup regi ster 14 dpsbkr14 8 8 4 to 5 pclk* 8 0008 c29fh system deep standby backup register 15 dpsbkr15 8 8 4 to 5 pclk* 8 0008 c2a0h system deep standby backup regi ster 16 dpsbkr16 8 8 4 to 5 pclk* 8 0008 c2a1h system deep standby backup regi ster 17 dpsbkr17 8 8 4 to 5 pclk* 8 0008 c2a2h system deep standby backup regi ster 18 dpsbkr18 8 8 4 to 5 pclk* 8 0008 c2a3h system deep standby backup regi ster 19 dpsbkr19 8 8 4 to 5 pclk* 8 0008 c2a4h system deep standby backup regi ster 20 dpsbkr20 8 8 4 to 5 pclk* 8 0008 c2a5h system deep standby backup regi ster 21 dpsbkr21 8 8 4 to 5 pclk* 8 0008 c2a6h system deep standby backup regi ster 22 dpsbkr22 8 8 4 to 5 pclk* 8 0008 c2a7h system deep standby backup regi ster 23 dpsbkr23 8 8 4 to 5 pclk* 8 0008 c2a8h system deep standby backup regi ster 24 dpsbkr24 8 8 4 to 5 pclk* 8 0008 c2a9h system deep standby backup regi ster 25 dpsbkr25 8 8 4 to 5 pclk* 8 0008 c2aah system deep standby backup regi ster 26 dpsbkr26 8 8 4 to 5 pclk* 8 0008 c2abh system deep standby backup regi ster 27 dpsbkr27 8 8 4 to 5 pclk* 8 0008 c2ach system deep standby backup regi ster 28 dpsbkr28 8 8 4 to 5 pclk* 8 0008 c2adh system deep standby backup regi ster 29 dpsbkr29 8 8 4 to 5 pclk* 8 0008 c2aeh system deep standby backup regi ster 30 dpsbkr30 8 8 4 to 5 pclk* 8 table 4.1 list of i/o registers (address order) (27 / 35) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0052ej0110 rev.1.10 page 79 of 146 feb 10, 2011 RX62N group, rx621 gr oup 4. i/o registers 0008 c2afh system deep standby backup regi ster 31 dpsbkr31 8 8 4 to 5 pclk* 8 0008 c400h rtc 64-hz counter r64cnt 8 8 2 to 3 pclk* 8 0008 c402h rtc second counter rseccnt 8 8 2 to 3 pclk* 8 0008 c404h rtc minute counter rmincnt 8 8 2 to 3 pclk* 8 0008 c406h rtc hour counter rhrcnt 8 8 2 to 3 pclk* 8 0008 c408h rtc day-of-week counter rwkcnt 8 8 2 to 3 pclk* 8 0008 c40ah rtc date counter rdaycnt 8 8 2 to 3 pclk* 8 0008 c40ch rtc month counter rmoncnt 8 8 2 to 3 pclk* 8 0008 c40eh rtc year counter ryrcnt 16 16 2 to 3 pclk* 8 0008 c410h rtc second alarm register rsecar 8 8 2 to 3 pclk* 8 0008 c412h rtc minute alarm register rminar 8 8 2 to 3 pclk* 8 0008 c414h rtc hour alarm register rhrar 8 8 2 to 3 pclk* 8 0008 c416h rtc day-of-week alarm register rwkar 8 8 2 to 3 pclk* 8 0008 c418h rtc date alarm register rdayar 8 8 2 to 3 pclk* 8 0008 c41ah rtc month alarm register rmonar 8 8 2 to 3 pclk* 8 0008 c41ch rtc year alarm register ryrar 16 16 2 to 3 pclk* 8 0008 c41eh rtc year alarm enable register ryraren 8 8 2 to 3 pclk* 8 0008 c422h rtc rtc control register 1 rcr1 8 8 2 to 3 pclk* 8 0008 c424h rtc rtc control register 2 rcr2 8 8 2 to 3 pclk* 8 0009 0200h to 0009 03ffh can0 mailbox registers 0 to 31 mb0 to mb031 128 8, 16, 32 2 to 3 pclk* 8 0009 0400h can0 mask register 0 mkr0 32 8, 16, 32 2 to 3 pclk* 8 0009 0404h can0 mask register 1 mkr1 32 8, 16, 32 2 to 3 pclk* 8 0009 0408h can0 mask register 2 mkr2 32 8, 16, 32 2 to 3 pclk* 8 0009 040ch can0 mask register 3 mkr3 32 8, 16, 32 2 to 3 pclk* 8 0009 0410h can0 mask register 4 mkr4 32 8, 16, 32 2 to 3 pclk* 8 0009 0414h can0 mask register 5 mkr5 32 8, 16, 32 2 to 3 pclk* 8 0009 0418h can0 mask register 6 mkr6 32 8, 16, 32 2 to 3 pclk* 8 0009 041ch can0 mask register 7 mkr7 32 8, 16, 32 2 to 3 pclk* 8 0009 0420h can0 fifo received id compare register 0 fidcr0 32 8, 16, 32 2 to 3 pclk* 8 0009 0424h can0 fifo received id compare register 1 fidcr1 32 8, 16, 32 2 to 3 pclk* 8 0009 0428h can0 mask invalid register mkivlr 32 8, 16, 32 2 to 3 pclk* 8 0009 042ch can0 mailbox interrupt enable register mier 32 8, 16, 32 2 to 3 pclk* 8 0009 0820h to 0009 083fh can0 message control registers 0 to 31 c0mctl0 to c0mctl031 8 8 2 to 3 pclk* 8 0009 0840h can0 control register ctlr 16 8, 16 2 to 3 pclk* 8 0009 0842h can0 status register str 16 8, 16 2 to 3 pclk* 8 0009 0844h can0 bit configuration register bcr 32 8, 16, 32 2 to 3 pclk* 8 0009 0848h can0 receive fifo control register rfcr 8 8 2 to 3 pclk* 8 0009 0849h can0 receive fifo pointer control register rfpcr 8 8 2 to 3 pclk* 8 0009 084ah can0 transmit fifo control register tfcr 8 8 2 to 3 pclk* 8 0009 084bh can0 transmit fifo pointer control register tfpcr 8 8 2 to 3 pclk* 8 0009 084ch can0 error interrupt enable register eier 8 8 2 to 3 pclk* 8 0009 084dh can0 error interrupt factor judge register eifr 8 8 2 to 3 pclk* 8 0009 084eh can0 receive error count register recr 8 8 2 to 3 pclk* 8 table 4.1 list of i/o registers (address order) (28 / 35) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0052ej0110 rev.1.10 page 80 of 146 feb 10, 2011 RX62N group, rx621 gr oup 4. i/o registers 0009 084fh can0 transmit error count register tecr 8 8 2 to 3 pclk* 8 0009 0850h can0 error code store register ecsr 8 8 2 to 3 pclk* 8 0009 0851h can0 channel search support register cssr 8 8 2 to 3 pclk* 8 0009 0852h can0 mailbox search status registe mssr 8 8 2 to 3 pclk* 8 0009 0853h can0 mailbox search mode registe msmr 8 8 2 to 3 pclk* 8 0009 0854h can0 time stamp registerr tsr 16 8, 16 2 to 3 pclk* 8 0009 0856h can0 acceptance filter support register afsr 16 8, 16 2 to 3 pclk* 8 0009 0858h can0 test control register tcr 8 8 2 to 3 pclk* 8 000a 0000h usb0 system configuration control register syscfg 16 16 3 to 4 pclk* 8 000a 0004h usb0 system configuration stat us register 0 syssts0 16 16 at least 9 pclk* 9 000a 0008h usb0 device state control register 0 dvstctr0 16 16 at least 9 pclk* 9 000a 0014h usb0 cfifo port register cfifo 16 8, 16 3 to 4 pclk* 8 000a 0018h usb0 d0fifo port register d0fifo 16 8, 16 3 to 4 pclk* 8 000a 001ch usb0 d1fifo port register d1fifo 16 8, 16 3 to 4 pclk* 8 000a 0020h usb0 cfifo port select register cfifosel 16 16 3 to 4 pclk* 8 000a 0022h usb0 cfifo port control register cfifoctr 16 16 3 to 4 pclk* 8 000a 0028h usb0 d0fifo port select register d0fifosel 16 16 3 to 4 pclk* 8 000a 002ah usb0 d0fifo port control register d0fifoctr 16 16 3 to 4 pclk* 8 000a 002ch usb0 d1fifo port select register d1fifosel 16 16 3 to 4 pclk* 8 000a 002eh usb0 d1fifo port control register d1fifoctr 16 16 3 to 4 pclk* 8 000a 0030h usb0 interrupt enable register 0 intenb0 16 16 at least 9 pclk* 9 000a 0032h usb0 interrupt enable register 1 intenb1 16 16 at least 9 pclk* 9 000a 0036h usb0 brdy interrupt enable register brdyenb 16 16 at least 9 pclk* 9 000a 0038h usb0 nrdy interrupt enable register nrdyenb 16 16 at least 9 pclk* 9 000a 003ah usb0 bemp interrupt enable register bempenb 16 16 at least 9 pclk* 9 000a 003ch usb0 sof output configuration register sofcfg 16 16 at least 9 pclk* 9 000a 0040h usb0 interrupt status register 0 intsts0 16 16 at least 9 pclk* 9 000a 0042h usb0 interrupt status register 1 intsts1 16 16 at least 9 pclk* 9 000a 0046h usb0 brdy interrupt enable register brdysts 16 16 at least 9 pclk* 9 000a 0048h usb0 nrdy interrupt status register nrdysts 16 16 at least 9 pclk* 9 000a 004ah usb0 bemp interrupt status register bempsts 16 16 at least 9 pclk* 9 000a 004ch usb0 frame number register frmnum 16 16 at least 9 pclk* 9 000a 004eh usb0 device state change register dvchgr 16 16 at least 9 pclk* 9 000a 0050h usb0 usb address register usbaddr 16 16 at least 9 pclk* 9 table 4.1 list of i/o registers (address order) (29 / 35) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0052ej0110 rev.1.10 page 81 of 146 feb 10, 2011 RX62N group, rx621 gr oup 4. i/o registers 000a 0054h usb0 usb request type register usbreq 16 16 at least 9 pclk* 9 000a 0056h usb0 usb request value register usbval 16 16 at least 9 pclk* 9 000a 0058h usb0 usb request index register usbindx 16 16 at least 9 pclk* 9 000a 005ah usb0 usb request length register usbleng 16 16 at least 9 pclk* 9 000a 005ch usb0 dcp configuration register dcpcfg 16 16 at least 9 pclk* 9 000a 005eh usb0 dcp maximum packet size register dcpmaxp 16 16 at least 9 pclk* 9 000a 0060h usb0 dcp control register dcpctr 16 16 at least 9 pclk* 9 000a 0064h usb0 pipe window select register pipesel 16 16 at least 9 pclk* 9 000a 0068h usb0 pipe configuration register pipecfg 16 16 at least 9 pclk* 9 000a 006ch usb0 pipe maximum packet si ze register pipemaxp 16 16 at least 9 pclk* 9 000a 006eh usb0 pipe cycle control register pipeperi 16 16 at least 9 pclk* 9 000a 0070h usb0 pipe 1 control register pipe1ctr 16 16 at least 9 pclk* 9 000a 0072h usb0 pipe 2 control register pipe2ctr 16 16 at least 9 pclk* 9 000a 0074h usb0 pipe 3 control register pipe3ctr 16 16 at least 9 pclk* 9 000a 0076h usb0 pipe 4 control register pipe4ctr 16 16 at least 9 pclk* 9 000a 0078h usb0 pipe 5 control register pipe5ctr 16 16 at least 9 pclk* 9 000a 007ah usb0 pipe 6 control register pipe6ctr 16 16 at least 9 pclk* 9 000a 007ch usb0 pipe 7 control register pipe7ctr 16 16 at least 9 pclk* 9 000a 007eh usb0 pipe 8 control register pipe8ctr 16 16 at least 9 pclk* 9 000a 0080h usb0 pipe 9 control register pipe9ctr 16 16 at least 9 pclk* 9 000a 0090h usb0 pipe 1 transaction counter enable register pipe1tre 16 16 at least 9 pclk* 9 000a 0092h usb0 pipe 1 transaction counter register pipe1trn 16 16 at least 9 pclk* 9 000a 0094h usb0 pipe 2 transaction counter enable register pipe2tre 16 16 at least 9 pclk* 9 000a 0096h usb0 pipe 2 transaction counter register pipe2trn 16 16 at least 9 pclk* 9 000a 0098h usb0 pipe 3 transaction counter enable register pipe3tre 16 16 at least 9 pclk* 9 000a 009ah usb0 pipe 3 transaction counter register pipe3trn 16 16 at least 9 pclk* 9 table 4.1 list of i/o registers (address order) (30 / 35) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0052ej0110 rev.1.10 page 82 of 146 feb 10, 2011 RX62N group, rx621 gr oup 4. i/o registers 000a 009ch usb0 pipe 4 transaction counter enable register pipe4tre 16 16 at least 9 pclk* 9 000a 009eh usb0 pipe 4 transaction counter register pipe4trn 16 16 at least 9 pclk* 9 000a 00a0h usb0 pipe 5 transaction counter enable register pipe5tre 16 16 at least 9 pclk* 9 000a 00a2h usb0 pipe 5 transaction counter register pipe5trn 16 16 at least 9 pclk* 9 000a 00d0h usb0 device address 0 configuration register devadd0 16 16 at least 9 pclk* 9 000a 00d2h usb0 device address 1 configuration register devadd1 16 16 at least 9 pclk* 9 000a 00d4h usb0 device address 2 configuration register devadd2 16 16 at least 9 pclk* 9 000a 00d6h usb0 device address 3 configuration register devadd3 16 16 at least 9 pclk* 9 000a 00d8h usb0 device address 4 configuration register devadd4 16 16 at least 9 pclk* 9 000a 00dah usb0 device address 5 configuration register devadd5 16 16 at least 9 pclk* 9 000a 0200h usb1 system configuration control register syscfg 16 16 3 to 4 pclk* 8 000a 0204h usb1 system configuration stat us register 0 syssts0 16 16 at least 9 pclk* 9 000a 0208h usb1 device state control register 0 dvstctr0 16 16 at least 9 pclk* 9 000a 0214h usb1 cfifo port register cfifo 16 8, 16 3 to 4 pclk* 8 000a 0218h usb1 d0fifo port register d0fifo 16 8, 16 3 to 4 pclk* 8 000a 021ch usb1 d1fifo port register d1fifo 16 8, 16 3 to 4 pclk* 8 000a 0220h usb1 cfifo port select register cfifosel 16 16 3 to 4 pclk* 8 000a 0222h usb1 cfifo port control register cfifoctr 16 16 3 to 4 pclk* 8 000a 0228h usb1 d0fifo port select register d0fifosel 16 16 3 to 4 pclk* 8 000a 022ah usb1 d0fifo port control register d0fifoctr 16 16 3 to 4 pclk* 8 000a 022ch usb1 d1fifo port select register d1fifosel 16 16 3 to 4 pclk* 8 000a 022eh usb1 d1fifo port control register d1fifoctr 16 16 3 to 4 pclk* 8 000a 0230h usb1 interrupt enable register 0 intenb0 16 16 at least 9 pclk* 9 000a 0232h usb1 interrupt enable register 1 intenb1 16 16 at least 9 pclk* 9 000a 0236h usb1 brdy interrupt enable register brdyenb 16 16 at least 9 pclk* 9 000a 0238h usb1 nrdy interrupt enable register nrdyenb 16 16 at least 9 pclk* 9 000a 023ah usb1 bemp interrupt enable register bempenb 16 16 at least 9 pclk* 9 000a 023ch usb1 sof output configuration register sofcfg 16 16 at least 9 pclk* 9 000a 0240h usb1 interrupt status register 0 intsts0 16 16 at least 9 pclk* 9 000a 0242h usb1 interrupt status register 1 intsts1 16 16 at least 9 pclk* 9 table 4.1 list of i/o registers (address order) (31 / 35) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0052ej0110 rev.1.10 page 83 of 146 feb 10, 2011 RX62N group, rx621 gr oup 4. i/o registers 000a 0246h usb1 brdy interrupt status register brdysts 16 16 at least 9 pclk* 9 000a 0248h usb1 nrdy interrupt status register nrdysts 16 16 at least 9 pclk* 9 000a 024ah usb1 bemp interrupt status register bempsts 16 16 at least 9 pclk* 9 000a 024ch usb1 frame number register frmnum 16 16 at least 9 pclk* 9 000a 024eh usb1 device state change register dvchgr 16 16 at least 9 pclk* 9 000a 0250h usb1 usb address register usbaddr 16 16 at least 9 pclk* 9 000a 0254h usb1 usb request type register usbreq 16 16 at least 9 pclk* 9 000a 0256h usb1 usb request value register usbval 16 16 at least 9 pclk* 9 000a 0258h usb1 usb request index register usbindx 16 16 at least 9 pclk* 9 000a 025ah usb1 usb request length register usbleng 16 16 at least 9 pclk* 9 000a 025ch usb1 dcp configuration register dcpcfg 16 16 at least 9 pclk* 9 000a 025eh usb1 dcp maximum packet size register dcpmaxp 16 16 at least 9 pclk* 9 000a 0260h usb1 dcp control register dcpctr 16 16 at least 9 pclk* 9 000a 0264h usb1 pipe window select register pipesel 16 16 at least 9 pclk* 9 000a 0268h usb1 pipe configuration register pipecfg 16 16 at least 9 pclk* 9 000a 026ch usb1 pipe maximum packet si ze register pipemaxp 16 16 at least 9 pclk* 9 000a 026eh usb1 pipe cycle control register pipeperi 16 16 at least 9 pclk* 9 000a 0270h usb1 pipe 1 control register pipe1ctr 16 16 at least 9 pclk* 9 000a 0272h usb1 pipe 2 control register pipe2ctr 16 16 at least 9 pclk* 9 000a 0274h usb1 pipe 3 control register pipe3ctr 16 16 at least 9 pclk* 9 000a 0276h usb1 pipe 4 control register pipe4ctr 16 16 at least 9 pclk* 9 000a 0278h usb1 pipe 5 control register pipe5ctr 16 16 at least 9 pclk* 9 000a 027ah usb1 pipe 6 control register pipe6ctr 16 16 at least 9 pclk* 9 000a 027ch usb1 pipe 7 control register pipe7ctr 16 16 at least 9 pclk* 9 000a 027eh usb1 pipe 8 control register pipe8ctr 16 16 at least 9 pclk* 9 000a 0280h usb1 pipe 9 control register pipe9ctr 16 16 at least 9 pclk* 9 table 4.1 list of i/o registers (address order) (32 / 35) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0052ej0110 rev.1.10 page 84 of 146 feb 10, 2011 RX62N group, rx621 gr oup 4. i/o registers 000a 0290h usb1 pipe 1 transaction counter enable register pipe1tre 16 16 at least 9 pclk* 9 000a 0292h usb1 pipe 1 transaction counter register pipe1trn 16 16 at least 9 pclk* 9 000a 0294h usb1 pipe 2 transaction counter enable register pipe2tre 16 16 at least 9 pclk* 9 000a 0296h usb1 pipe 2 transaction counter register pipe2trn 16 16 at least 9 pclk* 9 000a 0298h usb1 pipe 3 transaction counter enable register pipe3tre 16 16 at least 9 pclk* 9 000a 029ah usb1 pipe 3 transaction counter register pipe3trn 16 16 at least 9 pclk* 9 000a 029ch usb1 pipe 4 transaction counter enable register pipe4tre 16 16 at least 9 pclk* 9 000a 029eh usb1 pipe 4 transaction counter register pipe4trn 16 16 at least 9 pclk* 9 000a 02a0h usb1 pipe 5 transaction counter enable register pipe5tre 16 16 at least 9 pclk* 9 000a 02a2h usb1 pipe 5 transaction counter register pipe5trn 16 16 at least 9 pclk* 9 000a 02d0h usb1 device address 0 configuration register devadd0 16 16 at least 9 pclk* 9 000a 02d2h usb1 device address 1 configuration register devadd1 16 16 at least 9 pclk* 9 000a 02d4h usb1 device address 2 configuration register devadd2 16 16 at least 9 pclk* 9 000a 02d6h usb1 device address 3 configuration register devadd3 16 16 at least 9 pclk* 9 000a 02d8h usb1 device address 4 configuration register devadd4 16 16 at least 9 pclk* 9 000a 02dah usb1 device address 5 configuration register devadd5 16 16 at least 9 pclk* 9 000a 0400h usb deep standby usb transceiver control/ pin monitor register dpusr0r 32 32 1 to 2pclk* 8 000a 0404h usb deep standby usb suspend/resume interrupt register dpusr1r 32 32 1 to 2pclk* 8 000c 0000h edmac edmac mode register edmr 32 32 4 to 5 iclk 000c 0008h edmac edmac transmit request register edtrr 32 32 4 to 5 iclk 000c 0010h edmac edmac receive request register edrrr 32 32 4 to 5 iclk 000c 0018h edmac transmit descriptor list start address register tdlar 32 32 4 to 5 iclk 000c 0020h edmac receive descriptor list start address register rdlar 32 32 4 to 5 iclk 000c 0028h edmac etherc/edmac status register eesr 32 32 4 to 5 iclk 000c 0030h edmac etherc/edmac status interrupt permission register eesipr 32 32 4 to 5 iclk 000c 0038h edmac transmit/receive status copy enable register trscer 32 32 4 to 5 iclk 000c 0040h edmac receive missed-frame counter register rmfcr 32 32 4 to 5 iclk 000c 0048h edmac transmit fifo threshold register tftr 32 32 4 to 5 iclk 000c 0050h edmac fifo depth register fdr 32 32 4 to 5 iclk 000c 0058h edmac receiving method control register rmcr 32 32 4 to 5 iclk table 4.1 list of i/o registers (address order) (33 / 35) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0052ej0110 rev.1.10 page 85 of 146 feb 10, 2011 RX62N group, rx621 gr oup 4. i/o registers 000c 0064h edmac transmit fifo underrun counter tfucr 32 32 4 to 5 iclk 000c 0068h edmac receive fifo overflow counter rfocr 32 32 4 to 5 iclk 000c 006ch edmac independent output signal setting register iosr 32 32 4 to 5 iclk 000c 0070h edmac flow control start fifo threshold setting register fcftr 32 32 4 to 5 iclk 000c 0078h edmac receive data padding insert register rpadir 32 32 4 to 5 iclk 000c 007ch edmac transmit interrupt setting register trimd 32 32 4 to 5 iclk 000c 00c8h edmac receive buffer write address register rbwar 32 32 4 to 5 iclk 000c 00cch edmac receive descriptor fetch address register rdfar 32 32 4 to 5 iclk 000c 00d4h edmac transmit buffer read address register tbrar 32 32 4 to 5 iclk 000c 00d8h edmac transmit descriptor fetch address register tdfar 32 32 4 to 5 iclk 000c 0100h etherc etherc mode register ecmr 32 32 4 to 5 iclk 000c 0108h etherc receive frame length register rflr 32 32 4 to 5 iclk 000c 0110h etherc etherc status register ecsr 32 32 4 to 5 iclk 000c 0118h etherc etherc interrupt enable register ecsipr 32 32 4 to 5 iclk 000c 0120h etherc phy interface register pir 32 32 4 to 5 iclk 000c 0128h etherc phy status register psr 32 32 4 to 5 iclk 000c 0140h etherc random number generation counter upper limit setting register rdmlr 32 32 4 to 5 iclk 000c 0150h etherc ipg register ipgr 32 32 4 to 5 iclk 000c 0154h etherc automatic pause frame register apr 32 32 4 to 5 iclk 000c 0158h etherc manual pause frame register mpr 32 32 4 to 5 iclk 000c 0160h etherc pause frame receive counter register rfcf 32 32 4 to 5 iclk 000c 0164h etherc automatic pause frame retransmit count register tpauser 32 32 4 to 5 iclk 000c 0168h etherc pause frame retransmit counter register tpausecr 32 32 4 to 5 iclk 000c 016ch etherc broadcast frame receive count setting register bcfrr 32 32 4 to 5 iclk 000c 01c0h etherc mac address high register mahr 32 32 4 to 5 iclk 000c 01c8h etherc mac address low register malr 32 32 4 to 5 iclk 000c 01d0h etherc transmit retry over counter register trocr 32 32 4 to 5 iclk 000c 01d4h etherc delayed collision detect counter register cdcr 32 32 4 to 5 iclk 000c 01d8h etherc lost carrier counter register lccr 32 32 4 to 5 iclk 000c 01dch etherc carrier not detect counter register cndcr 32 32 4 to 5 iclk 000c 01e4h etherc crc error frame receive counter register cefcr 32 32 4 to 5 iclk 000c 01e8h etherc frame receive error counter register frecr 32 32 4 to 5 iclk 000c 01ech etherc too-short frame receive counter register tsfrcr 32 32 4 to 5 iclk 000c 01f0h etherc too-long frame receive counter register tlfrcr 32 32 4 to 5 iclk 000c 01f4h etherc residual-bit frame receive counter register rfcr 32 32 4 to 5 iclk 000c 01f8h etherc multicast address frame receive counter register mafcr 32 32 4 to 5 iclk 007f c402h flash flash mode register fmodr 8 8 2 to 3 pclk* 8 007f c410h flash flash access status register fastat 8 8 2 to 3 pclk* 8 table 4.1 list of i/o registers (address order) (34 / 35) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0052ej0110 rev.1.10 page 86 of 146 feb 10, 2011 RX62N group, rx621 gr oup 4. i/o registers note 1. when the same output trigger is specified for pulse out put groups 2 and 3 by the ppg0.pcr setting, the ppg0.ndrh address is 000881ech. when different output triggers are specified, the ppg0.ndrh2 addresses for pulse output groups 2 and 3 are 000881eeh and 000881ech, respectively. note 2. when the same output trigger is specified for pulse output groups 0 and 1 by the ppg0.pcr setting, the ppg0.ndrl address is 000881edh. when different output triggers are specified, the ppg0.ndrl2 addresses for pulse output groups 0 and 1 are 000881efh and 000881edh, respectively. note 3. when the same output trigger is specified for pulse out put groups 6 and 7 by the ppg1.pcr setting, the ppg1.ndrh address is 000881fch. when different output triggers are specified, the ppg1.ndrh2 addresses for pulse output groups 6 and 7 are 000881feh and 000881fch, respectively. note 4. when the same output trigger is specified for pulse output groups 4 and 5 by the ppg1.pcr setting, the ppg1.ndrl address is 000881fdh. when different output triggers are specified, the ppg1.ndrl2 addresses for pulse output groups 4 and 5 are 000881ffh and 000881fdh, respectively. note 5. this register is not supported by the 145-pin tflga or 144-pin lqfp version. note 6. this register is not su pported by the 100-pin lqfp version. note 7. this register is not supported by the 85-pin tflga version. note 8. the number of access states depends on the number of divi ded cycles for clock synchronizati on (0 to 1 pclk, 0 to 1 bclk) . note 9. access may be disabled if a regi ster is accessed during the usb operation. 007f c411h flash flash access error interrupt enable register faeint 8 8 2 to 3 pclk* 8 007f c412h flash flash ready interrupt enable register frdyie 8 8 2 to 3 pclk* 8 007f c440h flash data flash read enable register0 dflre0 16 16 2 to 3 pclk* 8 007f c442h flash data flash read enable register1 dflre1 16 16 2 to 3 pclk* 8 007f c450h flash data flash programming/erasure enable register0 dflwe0 16 16 2 to 3 pclk* 8 007f c452h flash data flash programming/erasure enable register1 dflwe1 16 16 2 to 3 pclk* 8 007f c454h flash fcu ram enable register fcurame 16 16 2 to 3 pclk* 8 007f ffb0h flash flash status register 0 fstatr0 8 8 2 to 3 pclk* 8 007f ffb1h flash flash status register 1 fstatr1 8 8 2 to 3 pclk* 8 007f ffb2h flash flash p/e mode entry register fentryr 16 16 2 to 3 pclk* 8 007f ffb4h flash flash protect register fprotr 16 16 2 to 3 pclk* 8 007f ffb6h flash flash reset register fresetr 16 16 2 to 3 pclk* 8 007f ffbah flash fcu command register fcmdr 16 16 2 to 3 pclk* 8 007f ffc8h flash fcu processing switch ing register fcpsr 16 16 2 to 3 pclk* 8 007f ffcah flash data flash blank check control register dflbccnt 16 16 2 to 3 pclk* 8 007f ffcch flash flash p/e status register fpestat 16 16 2 to 3 pclk* 8 007f ffceh flash data flash blank check st atus register dflbcstat 16 16 2 to 3 pclk* 8 007f ffe8h flash peripheral clock notific ation register pckar 16 16 2 to 3 pclk* 8 table 4.1 list of i/o registers (address order) (35 / 35) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01uh0033jj0110 rev.1.10 page 87 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics 5. electrical characteristics 5.1 absolute maximum ratings caution: permanent damage to the lsi may result if absolute maximum ratings are exceeded. note 1. ports 00 to 02, 07, ports 12, 13, 16, 17, ports 20, 21, and port 33 are 5 v tolerant. note 2. connect avcc to vcc. when neither the a/d converter nor the d/a converter is in use, do not leave the avcc, vrefh, avss, and vrefl pins open. connect the avcc and vrefh pins to vcc, and the avss and vrefl pins to vss, respectively. table 5.1 absolute maximum ratings item symbol value unit power supply voltage vcc pllvcc vcc_usb -0.3 to +4.6 v input voltage (except for ports 00 to 02, 07, ports 12, 13, 16, 17, ports 20, 21, port 33) v in -0.3 to vcc+0.3 v input voltage (ports 00 to 02, 07, ports 12, 13, 16, 17, ports 20, 21, port 33 *1 ) v in -0.3 to +5.8 v reference power supply voltage v ref -0.3 to vcc+0.3 v analog power supply voltage avcc *2 -0.3 to +4.6 v analog input voltage v an -0.3 to vcc+0.3 v operating temperature t opr -40 to +85 c storage temperature t stg -55 to +125 c
r01uh0033jj0110 rev.1.10 page 88 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics 5.2 dc characteristics table 5.2 dc characteristics (1) conditions: vcc = pllvcc = avcc = vcc_usb = 2.7 to 3.6v, vrefh = 2.7v to avcc vss = pllvss = avss = vrefl = vss_usb = 0v t a = -40 to +85 ? c item symbol min. typ. max. unit test conditions schmitt trigger input voltage *2 irq input pin *1 mtu input pin *1 tmr input pin *1 sci input pin *1 adtrg input pin *1 res#, nmi v ih vcc 0.8 ? vcc+0.3 v v il -0.3 ? vcc 0.2 v t vcc 0.06 ? ? riic input pin (except for smbus) v ih vcc 0.7 ? 5.8 v il -0.3 ? vcc 0.3 v t vcc 0.05 ? ? ports 00 to 02, 07 ports 12, 13, 16, 17 ports 20, 21 port 33 v ih vcc 0.8 ? 5.8 v il -0.3 ? vcc 0.2 ports 03, 05, 10, 11, 14, 15 ports 22 to 27 ports 30 to 32, 34, 35 ports 4 to g other input pins v ih vcc 0.8 ? vcc+0.3 v il -0.3 ? vcc 0.2 input high voltage (except schmitt trigger input pin) md pin, emle v ih vcc 0.9 ? vcc+0.3 v extal, rspi, etherc exdmac, wait#, tck vcc 0.8 ? vcc+0.3 xcin vcc 0.8 ? vcc+0.3 d0 to d31 vcc 0.7 ? vcc+0.3 riic (smbus) 2.1 ? vcc+0.3 input low voltage (except schmitt trigger input pin) md pin, emle v il -0.3 ? vcc 0.1 v extal, rspi, etherc exdmac, wait#, tck -0.3 ? vcc 0.2 xcin -0.3 ? vcc0.2 d0 to d31 -0.3 ? vcc0.3 riic (smbus) -0.3 ? 0.8
r01uh0033jj0110 rev.1.10 page 89 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics table 5.3 dc characteristics (2) conditions: vcc = pllvcc = avcc = vcc_usb = 2.7 to 3.6v, vrefh = 2.7v to avcc vss = pllvss = avss = vrefl = vss_usb = 0v t a = -40 to +85 ? c item symbol min. typ. max. unit test conditions output high voltage all output pins v oh vcc-0.5 ? ? v i oh = -1ma output low voltage all output pins (except for riic pins) v ol ??0 . 5vi ol = 1.0ma riic pins ? ? 0.4 v i ol = 3.0ma ??0.6 i ol = 6.0ma riic pins (only p12 and p13 in channel 0) v ol ??0 . 4vi ol = 15.0ma (icfer.fmpe = 1) ?0.4? i ol = 20.0ma (icfer.fmpe = 1) input leakage current res#, md pin, emle, nmi | i in |? ? 1.0av in = 0v v in = vcc three-state leakage current (off state) ports 03, 05, 10, 11, 14, 15 ports 22 to 27 ports 30 to 32, 34, 35 ports 4 to g | i tsi | ? ? 1.0 a v in = 0v v in = vcc ports 00 to 02, 07, 12, 13 ports 16, 17, 20, 21, 33 ??5.0 input pull-up mos current ports 9 to e, g -i p 10 ? 300 a vcc = 2.7 to 3.6v v in = 0v input capacitance all input pins (except for ports 12, 13, 20, 21 ports 40 to 47, and emle) c in ? ? 15 pf v in = 0v f = 1mhz t a = 25c ports 12, 13, 20, 21, ports 40 to 47, emle ??3 0
r01uh0033jj0110 rev.1.10 page 90 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics note 1. this does not include the pins, which are multiplexed as ports 00 to 02, 07, ports 12, 13, 16, 17, ports 20, 21, and por t 33 for 5 v tolerant. note 2. supply current values are with all output pins unloaded and all input pull-up moss in the off state. note 3. measured with clocks suppl ied to the peripheral functions. this does not include the bgo operation. note 4. icc depends on f (iclk) as follows. (iclk: pclk: bclk = 8 : 4: 2) icc max. = 0.89 x f + 11 (max.) icc typ. = 0.43 x f + 5 (normal operati on, peripheral functi on: clocks supplied) icc typ. = 0.30 x f + 5 (normal operation, peripheral function: clocks not supplied) icc max. = 0.48 x f + 12 (sleep mode) note 5. this does not include the bgo operation. note 6. incremented if data is written to or erased from th e rom or data flash for data storage during the program execution. note 7. the values are for reference. table 5.4 dc characteristics (3) conditions: vcc = pllvcc = avcc = vcc_usb = 2.7 to 3.6v, vrefh = 2.7v to avcc vss = pllvss = avss = vrefl = vss_usb = 0v t a = -40 to +85 ? c item symbol min. typ. max. unit test conditions supply current *2 in operation max. *3 i cc *4 ?? 100 ma iclk = 100mhz pclk = 50mhz bclk = 50mhz peripheral function: clocks supplied *5 ?48? peripheral function clocks not supplied *5 ?15? sleep ? 20 60 all-module-clock-stop mode *7 ?1428 standby mode software standby mode ? 0.12 3.0 ma deep software standby mode rtc in operation ram, usb retained ?30 206 a ram, usb power supply halted ?26 66 a rtc halted ram, usb retained ?25 200 a ram, usb power supply halted ?21 60 a analog power supply current during 12-bit a/d conversion (per unit) ai cc ?2.53.0 ma during 10-bit a/d conversion (per unit) ? 0.8 1.2 ma during d/a conversion (per unit) ? 0.3 2.0 a idle (all units) ? 30 35 a reference power supply current during 12-bit a/d conversion (per unit) ai cc ?0.50.7 ma during 10-bit a/d conversion (per unit) ? 0.06 0.1 ma during d/a conversion (per unit) ? 0.6 1.0 ma idle (all units) ? 0.4 0.6 ma ram standby voltage v ram 2.48 ? ? v vcc rising gradient svcc ? ? 20 ms/v
r01uh0033jj0110 rev.1.10 page 91 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics caution: to protect the lsi's reliabil ity, the output current values should not exceed the permissible output current. table 5.5 permissible output currents conditions: vcc = pllvcc = avcc = vcc_usb = 2.7 to 3.6v, vrefh = 2.7v to avcc vss = pllvss = avss = vrefl = vss_usb = 0v t a = -40 to +85 ? c item symbol min. typ. max. unit permissible output low current (average value per pin) all output pins except for riic pins i ol ??2.0ma riic pins (icfer.fmpe = 0) i ol ??6.0 ma riic pins (icfer.fmpe = 1) i ol ??20.0 ma permissible output low current (max. value per pin) all output pins except for riic pins i ol ??4.0ma riic pins (icfer.fmpe = 0) i ol ??6.0 ma riic pins (icfer.fmpe = 1) i ol ??20.0 ma permissible output low current (total) total of all output pins i ol ??80ma permissible output high current (average value per pin) all output pins (except for usb_dpupe pin) -i oh ??2.0ma usb_dpupe pin -i oh ??3.0ma permissible output high current (max. value per pin) all output pins -i oh ??4.0ma permissible output high current (t otal) total of all output pins -i oh ??80ma
r01uh0033jj0110 rev.1.10 page 92 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics 5.3 ac characteristics note 1. note 1:the iclk must run at a frequency of at least 12.5 mhz if the ethernet controller is in use. note 2. note 2:the pclk must run at a frequency of at least 24 mhz if the usb is in use. note 1. the iclk must run at a frequency of at least 12.5 mhz if the ethernet controller is in use. note 2. the pclk must run at a frequency of at least 24 mhz if the usb is in use. table 5.6 operation frequency value [176-pin lfbga/145-pin tflga/144-pin lqfp] conditions: vcc = pllvcc = avcc = vcc_usb = 2.7 to 3.6v, vrefh = 2.7v to avcc vss = pllvss = avss = vrefl = vss_usb = 0v iclk = 8 to 100mhz, pclk = 8 to 50mhz, bclk = 8 to 100mhz, sdclk = 8 to 50mhz t a = -40 to +85 ? c item symbol min. typ. max. unit operation frequency system clock (iclk) f 8 *1 ? 100 mhz peripheral module clock (pclk) 8 *2 ?5 0 external bus clock (bclk) 8 ? 100 bclk pin output 8 ? 50 sdram clock (sdclk) 8 ? 50 sdclk pin output 8 ? 50 table 5.7 operation frequency value [100-pin lqfp/85-pin tflga] conditions: vcc = pllvcc = avcc = vcc_usb = 2.7 to 3.6v, vrefh = 2.7v to avcc vss = pllvss = avss = vrefl = vss_usb = 0v iclk = 8 to 100mhz, pclk = 8 to 50mhz, bclk = 8 to 50mhz t a = -40 to +85 ? c item symbol min. typ. max. unit operation frequency system clock (iclk) f 8 *1 ? 100 mhz peripheral module clock (pclk) 8 *2 ?5 0 external bus clock (bclk) 8 ? 50 bclk pin output 8 ? 25
r01uh0033jj0110 rev.1.10 page 93 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics 5.3.1 clock timing table 5.8 clock timing conditions: vcc = pllvcc = avcc = vcc_usb = 2.7 to 3.6v, vrefh = 2.7v to avcc vss = pllvss = avss = vrefl = vss_usb = 0v t a = -40 to +85 ? c item symbol min. max. unit test conditions bclk pin output cycle time [176-pin lfbga/145-pin tflga/144-pin lqfp] t bcyc 20 125 ns figure 5.1 bclk pin output cycle time [100-pin lqfp/85-pin tflga] t bcyc 40 125 ns bclk pin output high pulse width t ch 5 ?ns bclk pin output low pulse width t cl 5 ?ns bclk pin output rising time t cr ? 5ns bclk pin output falling time t cf ? 5ns sdclk pin output cycle time t sdcyc 20 125 ns sdclk pin output high pulse width t ch 5 ?ns sdclk pin output low pulse width t cl 5 ?ns sdclk pin output rising time t cr ? 5ns sdclk pin output falling time t cf ? 5ns oscillation settling time after reset (crystal) t osc1 10 ? ms figure 5.2 oscillation settling time after leaving software standby mode (crystal) t osc2 10 ? ms figure 5.3 oscillation settling time after leaving deep software standby mode (crystal) t osc3 10 ? ms figure 5.4 extal external clock output delay settling time t dext 1 ? ms figure 5.2 extal external clock input low pulse width t exl 35.71 ? ns figure 5.5 extal external clock input high pulse width t exh 35.71 ?ns extal external clock rising time t exr ? 5ns extal external clock falling time t exf ? 5ns xcin sub-clock oscilla tion settling time t subosc 2 ? s figure 5.6 xcin sub-clock oscillation frequency f sub 32.768 ?khz on-chip oscillator (iwd tclk) oscillation frequency f iwdtclk 62.5 187.5 khz
r01uh0033jj0110 rev.1.10 page 94 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics figure 5.1 bclk pin output, sdclk pin output timing figure 5.2 oscillation settling timing figure 5.3 oscillation settling timing after soft ware standby mode t ch t bcyc , t sdcyc t cf t cl t cr test conditions: v oh = vcc x 0.7, v ol = vcc x 0.3, i oh = -1.0ma, i ol = 1.0ma, c = 30pf bclk pin output, sdclk pin output t osc1 t dext vcc extal res# iclk software standby mode (power-down mode) irq exception handling irqmd[1:0] = 10b ssby = 1 wait instruction oscillation settling time t osc2 irq exception handling 01 10 ssby irqcrn.irqmd[1:0] irq iclk oscillator
r01uh0033jj0110 rev.1.10 page 95 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics figure 5.4 oscillation settling timi ng after deep so ftware standby mode invalid by the internal reset irq exception handling dirqneg = 1 ssby = 1 deep software standby mode (power-down mode) reset exception handling oscillation settling time t osc3 wait instruction when iokeep=l operating when iokeep=h oscillator iclk irq irq interrupt dirqnf set request set dirqneg bit set dpsby bit set iokeep bit cleared set l i/o port operating retained iokeep bit i/o port operating retained operating dpsrstf flag internal reset l h
r01uh0033jj0110 rev.1.10 page 96 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics figure 5.5 extal external input clock timing figure 5.6 xcin sub-clock oscillation settling time t exf vcc0.5 extal t exh t exl t exr xcin vcc t subosc oscillation settling time
r01uh0033jj0110 rev.1.10 page 97 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics 5.3.2 control signal timing note 1. do not allow a reset by the signal on the res# pin during programming or erasure of the rom or data-flash memory or duri ng blank checking of the data-flash memory. for details, see secti on 37.13, usage notes, in section 37., rom (flash memory for code storage). note 2. both the time and the number of cycles should satisfy the specifications. note 3. this is to specify the fcu reset and the wdt reset. note 4. t icyc : iclk cycles figure 5.7 reset input timing figure 5.8 nmi interrupt input timing figure 5.9 irq in terrupt in put timing table 5.9 control signal timing conditions: vcc = pllvcc = avcc = vcc_usb = 2.7 to 3.6v, vrefh = 2.7v to avcc vss = pllvss = avss = vrefl = vss_usb = 0v t a = -40 to +85 ? c item symbol min. max. unit test conditions res# pulse width (except for programming or erasure of the rom or data-flash memory or blank checking of the data-flash memory *1 ) t resw *2 20 ? t icyc figure 5.7 1.5 ? s internal reset time *3 t resw2 35 ? s nmi pulse width t nmiw 200 ? ns figure 5.8 irq pulse width t irqw 200 ? ns figure 5.9 res# t resw nmi t nmiw irq t irqw
r01uh0033jj0110 rev.1.10 page 98 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics 5.3.3 bus timing table 5.10 bus timing [176-pin lfbga/145-pin tflga/144-pin lqfp] conditions: vcc = pllvcc = avcc = vcc_usb = 2.7 to 3.6v, vrefh = 2.7v to avcc vss = pllvss = avss = vrefl = vss_usb = 0v iclk = 8 to 100mhz, bclk = 8 to 100mhz, sdclk = 8 to 50mhz t a = -40 to +85 ? c output load conditions: v oh = vcc0.5, v ol = vcc0.5, i oh = -1.0ma, i ol = 1.0ma, c = 30pf item symbol min. max. unit test conditions address delay time t ad ?15ns figure 5.10 to figure 5.13 byte control delay time t bcd ?15ns cs# delay time t csd ?15ns rd# delay time t rsd ?15ns read data setup time t rds 15 ? ns read data hold time t rdh 0.0 ? ns wr# delay time t wrd ?15ns write data delay time t wdd ?15ns write data hold time t wdh 0?n s wait# setup time t wts 15 ? ns figure 5.14 wait# hold time t wth 0.0 ? ns address delay time 2 (sdram) t ad2 11 5n s figure 5.22 to figure 5.28 cs# delay time 2 (sdram) t csd2 11 5n s dqm delay time (sdram) t dqmd 11 5n s cke delay time (sdram) t cked 11 5n s read data setup time 2 (sdram) t rds2 12 ? ns read data hold time 2 (sdram) t rdh2 0?n s write data delay time 2 (sdram) t wdd2 ?15ns write data hold time 2 (sdram) t wdh2 1?n s we# delay time (sdram) t wed 11 5n s ras# delay time (sdram) t rasd 11 5n s cas# delay time (sdram) t casd 11 5n s
r01uh0033jj0110 rev.1.10 page 99 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics table 5.11 bus timing [100-pin lqfp/85-pin tflga] conditions: vcc = pllvcc = avcc = vcc_usb = 2.7 to 3.6v, vrefh = 2.7v to avcc vss = pllvss = avss = vrefl = vss_usb = 0v iclk = 8 to 100mhz, pclk = 8 to 50mhz, bclk = 8 to 50mhz t a = -40 to +85 ? c output load conditions: v oh = vcc 0.5, v ol = vcc 0.5, i oh = -1.0ma, i ol = 1.0ma, c = 30pf item symbol min. max. unit test conditions address delay time t ad ? 30 ns figure 5.10 to figure 5.13 byte control delay time t bcd ?3 0 n s cs# delay time t csd ?3 0 n s rd# delay time t rsd ?3 0 n s read data setup time t rds 15 ? ns read data hold time t rdh 0.0 ? ns wr# delay time t wrd ?3 0 n s write data delay time t wdd ?3 5 n s write data hold time t wdh 0? n s wait# setup time t wts 15 ? ns figure 5.14 wait# hold time t wth 0.0 ? ns
r01uh0033jj0110 rev.1.10 page 100 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics figure 5.10 external bus timing/norma l read cycle (bus clock synchronized) a23 to a1 cs7# to cs0# t ad bclk a23 to a0 d31 to d0 (read) byte write strobe mode 1-write strobe mode bc3# to bc0# common to both byte write strobe mode and 1-write strobe mode t bcd t csd t csd rd# (read) t rsd t rsd t ad t rdh t rds t ad t ad t bcd t w1 t w2 t end t n1 t h rdon:1 csrwait:2 csroff:1 cson:0
r01uh0033jj0110 rev.1.10 page 101 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics figure 5.11 external bus timing/norma l write cycle (bus clock synchronized) a23 to a1 cs7# to cs0# t ad bclk a23 to a0 byte write strobe mode 1-write strobe mode bc3# to bc0# common to both byte write strobe mode and 1-write strobe mode t bcd t csd t csd t ad t ad t ad t bcd d31 to d0 (write) wr3# to wr0#, wr# (write) t wrd t wrd t wdh t wdd t w1 t w2 t end t n1 t h wron:1 wdon:1* 1 cswwait:2 cswoff:1 wdoff:1* 1 cson:0 note1: be sure to specify wdon a nd wdoff as at least one cycle o f bclk.
r01uh0033jj0110 rev.1.10 page 102 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics figure 5.12 external bus timing/pag e read cycle (bus clock synchronized) figure 5.13 external bu s timing/page write cycle (bus clock synchronized) a23 to a1 cs7# to cs0# t ad bclk a23 to a0 d31 to d0 (read) byte write strobe mode 1-write strobe mode bc3# to bc0# common to both byte write strobe mode and 1-write strobe mode t bcd t csd t csd rd# (read) t rsd t rsd t rdh t rds t ad t bcd t w1 t w2 t end t pw1 t pw2 t ad t ad t rsd t rsd t rdh t rds t rsd t rsd t rdh t rds t end t pw1 t pw2 t end t n1 t h t ad t ad t ad t ad rdon:1 csrwait:2 csroff:1 t rsd t rsd t rdh t rds t ad t ad csprwait:2 t pw1 t pw2 t end rdon:1 csprwait:2 rdon:1 csprwait:2 rdon:1 cson:0 a23 to a1 cs7# to cs0# t ad bclk a23 to a0 byte write strobe mode 1-write strobe mode bc3# to bc0# common to both byte write strobe mode and 1-write strobe mode t bcd t csd t csd t ad t bcd t w1 d31 to d0 (write) wr3# to wr0#, wr# (write) t wrd t wrd t wdh t wdd t w2 t end t pw1 t pw2 t ad t ad t wrd t wrd t wdh t wdd t wrd t wrd t wdh t wdd t dw1 t end t pw1 t pw2 t end t n1 t h t dw1 t ad t ad t ad t ad wron:1 wdon:1* 1 cswwait:2 cspwwait:2 wdoff:1* 1 cspwwait:2 wdoff:1* 1 cswoff:1 wdoff:1* 1 cson:0 note1: be sure to specify wdo n and wdoff as at least one cycle of bclk. wron:1 wdon:1* 1 wron:1 wdon:1* 1
r01uh0033jj0110 rev.1.10 page 103 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics figure 5.14 external bus timing/external wait control t wts t wth t wts t wth csrwait:3 cswwait:3 bclk a23 to a0 cs7# to cs0# rd# (read) wr# (write) wait# t w1 t w2 (t end )t end t w3 t n1 t h external wait
r01uh0033jj0110 rev.1.10 page 104 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics figure 5.15 sdram spa ce single read bus timing t ad2 sdclk a18 to a0 sdcs# ap* dqmn d31 to d0 ras# cas# we# cke note 1: address pins for output of the precharge-setting command (precharge-sel) for sdram. t dqmd (high) row address column address sdram command act rd pra t ad2 t csd2 t rasd t ad2 t ad2 t csd2 t rasd t ad2 t ad2 t csd2 t rasd t ad2 t ad2 t csd2 t rasd t wed t wed t csd2 t csd2 t casd t casd t rds2 t rdh2 pra command
r01uh0033jj0110 rev.1.10 page 105 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics figure 5.16 sdram spa ce single write bus timing t ad2 sdclk a18 to a0 sdcs# ap* 1 dqmn d31 to d0 ras# cas# we# cke note 1: address pins for output of the precharge-setting comman d (precharge-sel) for sdram. t dqmd (high) row address column address sdram command act wr pra t ad2 t csd2 t rasd t wed t casd t wdd2 t ad2 t ad2 t csd2 t rasd t ad2 t ad2 t csd2 t rasd t ad2 t ad2 t csd2 t rasd t csd2 t csd2 t casd t wed t wed t wed t wdh2 pra command
r01uh0033jj0110 rev.1.10 page 106 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics figure 5.17 sdram space multiple read bus timing sdclk note 1: address pins for output of the precharge-setting command (precharge-sel) for sdram. act rd rd rd rd pra a18 to a0 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 ap* 1 sdcs# ras# cas# we# cke dqmn d31 to d0 c1 c2 c3 row address c0 (column address) t ad2 t ad2 t ad2 t ad2 t ad2 t csd2 t csd2 t csd2 t csd2 t csd2 t ras d t ras d t ras d t ras d t ras d t cas d t cas d t cas d t wed t wed high t dqmd t dqmd t rds2 t rdh2 t rds2 t rdh2 pra command
r01uh0033jj0110 rev.1.10 page 107 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics figure 5.18 sdram space multiple write bus timing act wr pra wr wr wr sdclk a18 to a0 ap* 1 sdcs# ras# cas# we# cke dqmn d31 to d0 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t csd2 t csd2 t csd2 t csd2 t csd2 t ras d t ras d t ras d t ras d t ras d t cas d t cas d t cas d t wed t wed high t dqmd t dqmd t wdd2 t wdh2 t wdd2 t wdh2 c1 c2 c3 row address c0 (column address) pra command note 1: address pins for output of the precharge-setting command (precharge-sel) for sdram.
r01uh0033jj0110 rev.1.10 page 108 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics figure 5.19 sdram space multiple read line stride bus timing r1 a18 to a0 sdclk sdcs# ap* 1 dqmn d31 to d0 ras# cas# we# cke sdram command note 1: address pins for output of the precharge-setting command (precharge-sel) for sdram. act rd rdrdrdpra act rd rdrdrdpra t casd t rasd t csd2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t ad2 t csd2 t csd2 t csd2 t csd2 t csd2 t csd2 t csd2 t rasd t rasd t rasd t rasd t rasd t casd t casd t rasd t rasd t casd t dqmd t rds2 t rdh2 t rds2 t rdh2 t rds2 t rdh2 t rds2 t rdh2 (high) row address c0 (column address 0) c1 c2 c3 c4 c5 c6 c7 pra command pra command t wed t wed t wed t wed
r01uh0033jj0110 rev.1.10 page 109 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics figure 5.20 sdram space mode register set bus timing a18 to a0 sdclk sdcs# ap* 1 dqmn d31 to d0 ras# cas# we# cke sdram command (hi-z) (high) t casd t rasd t csd2 t ad2 mrs t ad2 t ad2 t ad2 t casd t rasd t csd2 note 1: address pins for output of the precharge-setting command (precharge-sel) for sdram. t wed t wed
r01uh0033jj0110 rev.1.10 page 110 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics figure 5.21 sdram spa ce self-refresh bus timing a18 to a0 (rfs) sdclk sdcs# ap* 1 dqmn d31 to d0 ras# cas# we# cke (hi-z) t cked (high) t casd t casd t casd t rasd t rasd t rasd t csd2 t csd2 t csd2 t ad2 t ad2 (rfa) ts (rfx) (rfa) t ad2 t ad2 t csd2 t csd2 t csd2 t csd2 t rasd t rasd t rasd t rasd t casd t casd t casd t casd t cked note 1: address pins for output of the precharge-setting command (precharge-sel) for sdram. sdram command t dqmd t dqmd
r01uh0033jj0110 rev.1.10 page 111 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics 5.3.4 exdmac timing figure 5.22 edreq0 and edreq1 input timing figure 5.23 edack0 and edack1 single -address transfer timing (for a cs area) figure 5.24 edack0 and edack1 sing le-address transfer timing (for sdram) table 5.12 exdmac timing conditions: vcc = pllvcc = avcc = vcc_usb = 2.7 to 3.6v, vrefh = 2.7v to avcc vss = pllvss = avss = vrefl = vss_usb = 0v iclk = 8 to 100mhz, pclk = 8 to 50mhz, bclk = 8 to 100mhz, sdclk = 8 to 50mhz t a = -40 to +85 ? c item symbol min. max. unit test conditions exdmac edreq setup time t edrqs 20 ? ns figure 5.22 edreq hold time t edrqh 5? ns edack delay time t edacd ? 15 ns figure 5.23 and figure 5.24 bclk t edrqs t edrqh edreq0 edreq1 edack0 edack1 t edacd bclk t edacd edack0 edack1 t edacd bclk t edacd
r01uh0033jj0110 rev.1.10 page 112 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics 5.3.5 timing of on-chi p peripheral modules table 5.13 timing of on-chip p eripheral modules (1) conditions: vcc = pllvcc = avcc = vcc_usb = 2.7 to 3.6v, vrefh = 2.7v to avcc vss = pllvss = avss = vrefl = vss_usb = 0v pclk = 8 to 50mhz t a = -40 to +85 ? c item symbol min. max. unit test conditions i/o ports output data delay time t pwd ? 40 ns figure 5.25 input data setup time t prs 25 ? ns input data hold time t prh 25 ? ns mtu2 output compare output delay time t tocd ?4 0n s figure 5.26 input capture input setup time t tics 20 ? ns input capture input pulse width (single-edge setting) t ticw 1.5 t pcyc ?ns input capture input pulse width (both-edge setting) t ticw 2.5 t pcyc ?ns timer input setup time t tcks 20 ? ns figure 5.27 timer clock pulse width (single-edge setting) t tckwh/l 1.5 t pcyc ?ns timer clock pulse width (both-edge setting) t tckwh/l 2.5 t pcyc ?ns timer clock pulse width (phase coefficient mode) t tckwh/l 2.5 t pcyc ?ns poe2 poe# input setup time t poes 50 ? ns figure 5.28 poe# input pulse width t poew 1.5 t pcyc ?ns ppg pulse output delay time t pod ?4 0n s figure 5.29 8-bit timer timer output delay time t tmod ?4 0n s figure 5.30 timer reset input setup time t tmrs 25 ? ns figure 5.31 timer clock input setup time t tmcs 25 ? ns figure 5.32 timer clock pulse width single-edge setting t tmcwh 1.5 t pcyc ?ns both-edge setting t tmcwl 2.5 t pcyc ?ns wdt overflow output delay time t wovd ?4 0n s figure 5.33
r01uh0033jj0110 rev.1.10 page 113 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics table 5.13 timing of on-chip peri pheral modules (1) (1/2) conditions: vcc = pllvcc = avcc = vcc_usb = 2.7 to 3.6v, vrefh = 2.7v to avcc vss = pllvss = avss = vrefl = vss_usb = 0v pclk = 8 to 50mhz t a = -40 to +85 ? c item symbol min. max. unit test conditions sci input clock cycle asynchronous t scyc 4 t pcyc ?n s figure 5.34 and figure 5.35 clock synchronous 6 t pcyc ? input clock pulse width t sckw 0.4 t scyc 0.6 t scyc ns input clock rise time t sckr ?2 0n s input clock fall time t sckf ?2 0n s output clock cycle asynchronous t scyc 4 t pcyc ?n s clock synchronous 6 t pcyc ? output clock pulse width t sckw 0.4 t scyc 0.6 t scyc ns output clock rise time t sckr ?2 0n s output clock fall time t sckf ?2 0n s transmit data delay time (clock synchronous) t txd ?4 0n s receive data setup time (clock synchronous) t rxs 40 ? ns receive data hold time (clock synchronous) t rxh 40 ? ns a/d converter 10-bit a/d converter trigger input setup time t trgs 25 ? ns figure 5.36 12-bit a/d converter trigger input setup time t trgs 25 ? ns
r01uh0033jj0110 rev.1.10 page 114 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics note 1. tpcyc: pclk cycle table 5.14 timing of on-chip peri pheral modules (2) (1/2) conditions: vcc = pllvcc = avcc = vcc_usb = 2.7 to 3.6v, vrefh = 2.7v to avcc vss = pllvss = avss = vrefl = vss_usb = 0v pclk = 8 to 50mhz t a = -40 to +85 ? c item symbol min. max. unit test conditions can transmit data delay time t ctxd ? 40.0 ns figure 5.37 receive data setup time t crxs 40.0 ? ns receive data hold time t crxh 40.0 ? ns rspi rspck clock cycle master t spcyc 2 4096 t pcyc *1 figure 5.38 slave 8 4096 rspck clock high pulse width master t spckwh (t spcyc -t spckr -t spckf ) / 2-3 ?ns slave (t spcyc -t spckr -t spckf ) / 2 ? rspck clock low pulse width master t spckwl (t spcyc -t spckr -t spckf ) / 2-3 ?ns slave (t spcyc -t spckr -t spckf ) / 2 ? rspck clock rise/fall time output [176-pin lfbga/ 145-pin tflga/ 144-pin lqfp] t spckr, t spckf ?5 n s output [100-pin lqfp/ 85-pin tflga] ?1 0 input ? 1 s
r01uh0033jj0110 rev.1.10 page 115 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics note 1. tpcyc: pclk cycle table 5.14 timing of on-chip periph eral modules (2) (2/2) conditions: vcc = pllvcc = avcc = vcc_usb = 2.7 to 3.6v, vrefh = 2.7v to avcc vss = pllvss = avss = vrefl = vss_usb = 0v pclk = 8 to 50mhz t a = -40 to +85 ? c item symbol min. max. unit test conditions rspi data input setup time master [176-pin lfbga/ 145-pin tflga/ 144-pin lqfp] t su 16 ? ns figure 5.39 to figure 5.42 master [100-pin lqfp/ 85-pin tflga] 30 ? slave 20-2 t pcyc ? data input hold time master t h 0?n s slave 20+2 t pcyc ? ssl setup time master t lead 18t spcyc slave 4 ? t pcyc ssl hold time master t lag 18t spcyc slave 4 ? t pcyc data output delay time master [176-pin lfbga/ 145-pin tflga/ 144-pin lqfp] t od ?2 0n s master [100-pin lqfp/ 85-pin tflga] ?3 0 slave [176-pin lfbga/ 145-pin tflga/ 144-pin lqfp] ?3 t pcyc +40 slave [100-pin lqfp/ 85-pin tflga] ?3 t pcyc +50
r01uh0033jj0110 rev.1.10 page 116 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics note 1. tpcyc: pclk cycle table 5.15 timing of on-chip p eripheral modules (3) conditions: vcc = pllvcc = avcc = vcc_usb = 2.7 to 3.6v, vrefh = 2.7v to avcc vss = pllvss = avss = vrefl = vss_usb = 0v pclk = 8 to 50mhz t a = -40 to +85 ? c item symbol min. max. unit test conditions rspi data output hold time master t oh 0 ? ns figure 5.39 to figure 5.42 slave 0 ? sucessive transmission delay time master t td t spcyc +2 t pcyc 8 t spcyc +2 t pcyc ns slave 4 t pcyc ? mosi, miso rise/fall time output [176-pin lfbga/ 145-pin tflga/ 144-pin lqfp] t dr, t df ?5n s output [100-pin lqfp/ 85-pin tflga] ?1 0 input ? 1 s ssl rise/fall time output [176-pin lfbga 145-pin tflga 144-pin lqfp] t sslr, t sslf ?5n s output [100-pin lqfp/ 85-pin tflga] ?1 0 input ? 1 s slave access time t sa ?4t pcyc figure 5.41 and figure 5.42 slave output release tim t rel ?3t pcyc
r01uh0033jj0110 rev.1.10 page 117 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics note: tiiccyc: riic inter nal reference clock (iic ) cycles note 1. the value in parentheses is used when icmr3.nf[1:0] are set to 11b while a digital filter is enabled with icfer.nfe = 1. note 2. cb indicates the total capacity of the bus line. table 5.16 timing of on-chip peri pheral modules (4) (1/2) conditions: vcc = pllvcc = avcc = vcc_usb = 2.7 to 3.6v, vrefh = 2.7v to avcc vss = pllvss = avss = vrefl = vss_usb = 0v pclk = 8 to 50mhz t a = -40 to +85 ? c t a = -40 to +85 ? c item symbol min. *1*2 max. unit test conditions riic (standard-mode, smbus) icfer.fmpe = 0 scl input cycle time t scl 6(12) t iiccyc + 1300 ? ns figure 5.43 scl input high pulse width t sclh 3(6) t iiccyc + 300 ? ns scl input low pulse width t scll 3(6) t iiccyc + 300 ? ns scl, sda input rising time t sr ? 1000 ns scl, sda input falling time t sf ? 300 ns scl, sda input spike pulse removal time t sp 0 1(4) t iiccy ns sda input bus free time t buf 3(6) t iiccyc + 300 ? ns start condition input hold time t stah tiiccyc + 300 ? ns re-start condition input setup time t stas 1000 ? ns stop condition input setup time t stos 1000 ? ns data input setup time t sdas t iiccyc + 50 ? ns data input hold time t sdah 0? ns scl, sda capacitive load c b ? 400 pf riic (fast-mode) scl input cycle time t scl 6(12) t iiccy + 600 ? ns scl input high pulse width t sclh 3(6) t iiccy + 300 ? ns scl input low pulse width t scll 3(6) t iiccy + 300 ? ns scl, sda input rising time t sr 20+0.1c b 300 ns scl, sda input falling time t sf 20+0.1c b 300 ns scl, sda input spike pulse removal time t sp 0 1(4) t iiccy ns sda input bus free time t buf 3(6) t iiccy + 300 ? ns start condition input hold time t stah t iiccy + 300 ? ns re-start condition input setup time t stas 300 ? ns stop condition input setup time t stos 300 ? ns data input setup time t sdas t iiccy + 50 ? ns data input hold time t sdah 0? ns scl, sda capacitive load c b ? 400 pf
r01uh0033jj0110 rev.1.10 page 118 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics note: tiiccyc: riic inter nal reference clock (iic ) cycles note 1. the value in parentheses is used when icmr3.nf[1:0] are set to 11b while a digital filter is enabled with icfer.nfe = 1. note 2. cb indicates the total capacity of the bus line. table 5.16 timing of on-chip peri pheral modules (4) (2/2) conditions: vcc = pllvcc = avcc = vcc_usb = 2.7 to 3.6v, vrefh = 2.7v to avcc vss = pllvss = avss = vrefl = vss_usb = 0v pclk = 8 to 50mhz t a = -40 to +85 ? cz t a = -40 to +85 ? c item symbol min. *1*2 max. unit test conditions riic (fast-mode+) icfer.fmpe = 1 scl input cycle time t scl 6(12) t iiccyc + 240 ? ns figure 5.43 scl input high pulse width t sclh 3(6) t iiccyc + 120 ? ns scl input low pulse width t scll 3(6) t iiccyc + 120 ? ns scl, sda input rising time t sr ? 120 ns scl, sda input falling time t sf ? 120 ns scl, sda input spike pulse removal time t sp 0 1(4) t iiccyc ns sda input bus free time t buf 3(6) t iiccyc + 120 ? ns start condition input hold time t stah t iiccyc + 120 ns re-start condition input setup time t stas 120 ? ns stop condition input setup time t stos 120 ? ns data input setup time t sdas t iiccyc + 20 ? ns data input hold time t sdah 0?n s scl, sda capacitive load c b ? 550 pf
r01uh0033jj0110 rev.1.10 page 119 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics note 1. rmii_txd_en, rmii_txd1, rmii_txd0 note 2. rmii_crs_dv, rmii_rxd1, rmii_rxd0, rmii_rx_er note 3. the user program must make setting s so that this stipulation is satisfied. table 5.17 timing of on-chip peri pheral modules (5) (1/2) conditions: vcc = pllvcc = avcc = vcc_usb = 2.7 to 3.6v, vrefh = 2.7v to avcc vss = pllvss = avss = vrefl = vss_usb = 0v pclk = 8 to 50mhz t a = -40 to +85 ? c item symbol min. max. unit test conditions etherc(rmii) ref50ck cycle time t ck 20 ? ns figure 5.44 to figure 5.47 ref50ck frequency typ. 50mhz ? ? 50 + 100ppm mhz ref50ck duty ? 35 65 % ref50ck rise/fall time t ckr/ckf 0.5 3.5 ns rmii_xxxx *1 output delay time t co 2.5 12.5 ns rmii_xxxx *2 setup time t su 3? ns rmii_xxxx *2 hold time t hd 1? ns rmii_xxxx *1*2 rise/fall time tr/tf 0.5 6 ns et_mdio setup time t mdios 10 ? ns figure 5.48 et_mdio hold time t mdioh 10 ? ns et_mdio output hold time *3 t mdiodh 5 ? ns figure 5.49 et_wol output delay time t wold 1 20 ns figure 5.50
r01uh0033jj0110 rev.1.10 page 120 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics note 1. rmii_txd_en, rmii_txd1, rmii_txd0 note 2. rmii_crs_dv, rmii_rxd1, rmii_rxd0, rmii_rx_er note 3. the user program must make setting s so that this stipulation is satisfied. table 5.17 timing of on-chip peri pheral modules (5) (2/2) conditions: vcc = pllvcc = avcc = vcc_usb = 2.7 to 3.6v, vrefh = 2.7v to avcc vss = pllvss = avss = vrefl = vss_usb = 0v pclk = 8 to 50mhz t a = -40 to +85 ? c item symbol min. max. unit test conditions etherc(mii) et_tx_clk cycle time t tcyc 40 ? ns ? et_tx_en output delay time t tend 1 20 ns figure 5.51 et_etxd0 to et_etxd3 output delay time t mtdd 120ns et_crs setup time t crss 10 ? ns et_crs hold time t crsh 10 ? ns et_col setup time t cols 10 ? ns figure 5.52 et_col hold time t colh 10 ? ns et_rx_clk cycle time t trcyc 40 ? ns ? et_rx_dv setup time t rdvs 10 ns figure 5.53 et_rx_dv hold time t rdvh 10 ? ns et_erxd0 to et_erxd3 setup time t mrds 10 ? ns et_erxd0 to et_erxd3 hold time t mrdh 10 ? ns et_rx_er setup time t rers 10 ? ns figure 5.54 et_rx_er hold time t resh 10 ? ns et_mdio setup time t mdios 10 ? ns figure 5.55 et_mdio hold time t mdioh 10 ? ns et_mdio utput hold time t mdiodh 5 ? ns figure 5.56 et_wol output delay time t wold 1 20 ns figure 5.57
r01uh0033jj0110 rev.1.10 page 121 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics figure 5.25 i/o port input/output timing figure 5.26 mtu2 input/output timing table 5.18 timing of on-chip p eripheral modules (6) conditions: vcc = pllvcc = avcc = vcc_usb = 2.7 to 3.6v, vrefh = 2.7v to avcc vss = pllvss = avss = vrefl = vss_usb = 0v pclk = 8 to 50mhz t a = -40 to +85 ? c item symbol min. typ. max. unit test conditions tck clock cycle time t tckcyc 100 ? ? ns figure 5.58 tck clock high pulse width t tckh 45??ns tck clock low pulse width t tckl 45??ns tck clock rising time t tckr ??5 ns tck clock falling time t tckf ??5 ns trst# pulse width t trstw 20??t tckcyc figure 5.59 tms setup time t tmss 20 ? ? ns figure 5.60 tms hold time t tmsh 20??ns tdi setup time t tdis 20??ns tdi hold time t tdih 20??ns tdo data delay time t tdod ??40ns pclk t1 t prs t2 t prh t pwd input port (read) output port (write) output compare output input capture input pclk t tocd t tics t ticw
r01uh0033jj0110 rev.1.10 page 122 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics figure 5.27 mtu2 clock input timing figure 5.28 poe# input timing figure 5.29 ppg output timing figure 5.30 8-bit timer output timing mtclka to mtclkh pclk t tckwl t tckwh t tcks t tcks poen# input pclk t poes t poew pclk po31 to po0 t pod pclk tmo0 to tmo3 t tmod
r01uh0033jj0110 rev.1.10 page 123 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics figure 5.31 8-bit timer reset input timing figure 5.32 8-bit timer clock input timing figure 5.33 wdt output timing figure 5.34 sck clock input timing pclk tmri0 to tmri3 t tmrs pclk tmci0 to tmci3 t tmcs t tmcs t tmcwl t tmcwh pclk wdtovf# t wovd t wovd t sckw t sckr t sckf t scyc sckn n = 0 to 3, 5, 6
r01uh0033jj0110 rev.1.10 page 124 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics figure 5.35 sci input/output timing: clock synchronous mode figure 5.36 a/d converter external trigg er input timing figure 5.37 can input/output timing t txd t rxs t rxh txdn rxdn sckn n = 0 to 3, 5, 6 t trgs adtrg0#-a/b adtrg1# pclk pclk t crxs crx0 ctx0 t crxh t ctxd
r01uh0033jj0110 rev.1.10 page 125 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics figure 5.38 rspi clock timing figure 5.39 rspi timing (master, cpha = 0) rspcka to rspckb master select output rspcka to rspckb slave select output t spckwh v oh v oh v ol v ol v oh v oh t spckwl t spckr t spckf v ol t spcyc t spckwh v ih v ih v il v il v ih v ih t spckwl t spckr t spckf v il t spcyc ssla3 to ssla0 sslb3 to sslb0 output rspcka to rspckb cpol=0 output rspcka to rspckb cpol=1 output misoa to misob input mosia to mosib output t dr t df t su t h t lead t td t lag t sslr t sslf t oh t od msb in data lsb in msb in msb out data lsb out idle msb out
r01uh0033jj0110 rev.1.10 page 126 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics figure 5.40 rspi timing (master, cpha = 1) figure 5.41 rspi timing (slave, cpha = 0) ssla3 to ssla0 sslb3 to sslb0 output rspcka to rspckb cpol=0 output rspcka to rspckb cpol=1 output misoa to misob input mosia to mosib output t dr t df t su t h t lead t td t lag t sslr t sslf t oh msb in data lsb in msb in msb out data lsb out idle msb out t od ssla0 sslb0 input rspcka to rspckb cpol=0 input rspcka to rspckb cpol=1 input mosia to mosib input misoa to misob output t dr t df t su t h t lead t td t lag t sa msb in data lsb in msb in msb out data lsb out msb in msb out t oh t od t rel
r01uh0033jj0110 rev.1.10 page 127 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics figure 5.42 rspi timing (slave, cpha = 1) figure 5.43 i2c bus int erface input/ou tput timing ssla0 sslb0 input rspcka to rspckb cpol=0 input rspcka to rspckb cpol=1 input misoa to misob output mosia to mosib input t dr t df t sa t oh t lead t td t lag t h lsb out (last data) data msb out msb in data lsb in msb in lsb out t su t od t rel msb out sda0, sda1 scl0, scl1 v ih v il t stah t sclh t scll p * 1 s * 1 t sf t sr t scl t sdah t sdas t stas t sp t stos p ? 1 t buf note1: s, p, and sr indicate the following conditions. s: start condition p: stop condition sr: restart condition test conditions v ih = v cc 0.7, v il = v cc 0.3 v ol = 0.6v, i ol = 6ma(icfer.fmpe = 0) v ol = 0.4v, i ol = 15ma(icfer.fmpe = 1) sr * 1
r01uh0033jj0110 rev.1.10 page 128 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics figure 5.44 ref50ck and rmii signal timing figure 5.45 rmii transmission timing figure 5.46 rmii reception timing (normal operation) tck ref50ck tckr tckf tco tsu thd signal signal signal transitions signal transitions signal transitions tf tr 90% 50% 10% 90% 50% 10% rmii_xxxx * 1 note1. rmii_txd_en rmii_txd1 rmii_txd0 rmii_crs_dv rmii_rxd1 rmii_rxd0 rmii_rx_er tck tco data tco sfd crc rmii_txd1 rmii_txd0 rmii_txd_en ref50ck preamble data sfd crc preamble thd tsu rmii_rxd1 rmii_rxd0 rmii_rx_er rmii_crs_dv ref50ck l thd tsu
r01uh0033jj0110 rev.1.10 page 129 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics figure 5.47 rmii recepti on timing (error occurrence) figure 5.48 mdio input timing (rmii) figure 5.49 mdio output timing (rmii) figure 5.50 wol output timing (rmii) data sfd xxxx preamble ref50ck tsu rmii_rxd1 rmii_rxd0 rmii_rx_er rmii_crs_dv thd et_mdc et_mdio t mdioh t mdios et_mdc et_mdio t mdiodh et_wol t wold ref50ck
r01uh0033jj0110 rev.1.10 page 130 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics figure 5.51 mii transmission timing (normal operation) figure 5.52 mii transmissi on timing (con flict occurrence) figure 5.53 mii reception timing (normal operation) data sfd crc t mtdd t tend t crss t crsh preamble et_col et_crs et_tx_er et_etxd[3:0] et_tx_en et_tx_clk jam t colh preamble et_col et_crs et_tx_er et_etxd[3:0] et_tx_en et_tx_clk t cols data sfd crc t mrdh preamble et_rx_er t rdvs t mrds t rdvn et_erxd[3:0] et_rx_dv et_rx_clk
r01uh0033jj0110 rev.1.10 page 131 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics figure 5.54 mii reception timing (error occurrence) figure 5.55 mdio input timing (mii) figure 5.56 mdio output timing(mii) figure 5.57 wol output timing(mii) data sfd xxxx t rerh preamble et_rx_er et_erxd[3:0] et_rx_dv et_rx_clk t rers et_mdc et_mdio t mdioh t mdios et_mdc et_mdio t mdiodh et_rx_clk et_wol t wold
r01uh0033jj0110 rev.1.10 page 132 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics figure 5.58 boundary scan tck timing figure 5.59 bounda ry scan trst# timing figure 5.60 boundary scan input/output timing tck t tckcyc t tckh t tckf t tckl t tckr res# trst# tck t trstw t tmss tck tms tdi tdo t tmsh t tdis t tdih t tdod
r01uh0033jj0110 rev.1.10 page 133 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics 5.4 usb characteristics figure 5.61 dp, dm output timing (full-speed) figure 5.62 test circuit (full-speed) table 5.19 internal usb full-speed characterist ics (dp, dm pin characteristics) conditions: vcc = pllvcc = avcc = vcc_usb = 3.0 to 3.6v, vrefh = 3.0v to avcc vss = pllvss = avss = vrefl = vcc_usb = 0v pclk = 24 to 50mhz t a = -40 to +85 ? c item symbol min. max. unit test conditions input characteristics input high level voltage v ih 2.0 ? v figure 5.61 and figure 5.62 input low level voltage v il ?0.8v differential input sensitivity v di 0.2 ? v dp ? dm differential commom mode range v cm 0.8 2.5 v output characteristics output high level voltage v oh 2.8 3.6 v i oh = -200a output low level voltage v ol 0.0 0.3 v i ol = 2ma cross over voltage v crs 1.3 2.0 v rising time t lr 420ns falling time t lf 420ns rising/falling time ratio t lr / t lf 90 111.11 % t lr / t lf output resistance z drv 28 44 ? rs = 22 ? included '3 ?'0 w /i w /u 9? 9? 9? 9? 9 &56 2evhuydwlrqsrlqw ? ? s) s) gs gp
r01uh0033jj0110 rev.1.10 page 134 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics 5.5 a/d conversion characteristics note 1. the conversion time includes the sampling time and the co mparison time. as the test condi tions, the number of sampling s tates is indicated. note 2. the scanning is not supported. note 3. the value in parentheses indicates the sampling time. note 1. the time conversion takes is the sum of the sampling interval and the time comparison takes (permissible signal-source impedance is up to 1.0 k ? ) table 5.20 10-bit a/d conversion characteristics conditions: vcc = pllvcc = avcc = vcc_usb = 2.7 to 3.6v, vrefh = 2.7v to avcc vss = pllvss = avss = vrefl = vss_usb = 0v pclk = 8 to 50mhz t a = -40 to +85 ? c item min. typ. max. unit test conditions resolution 10 10 10 bits conversion time *1 (pclk = 50-mhz operation) with 0.1-f external capacitor when the capacitor is charged enough *2 0.8 (0.3) *3 ?? ssampling 15 states without external capacitor permissible signal source impedance (max.) = 1.0 k ? 1.0 (0.5) *3 ?? sampling 25 states permissible signal source impedance (max.) = 5.0 k ? 2.6 (2.1) *3 ?? sampling 105 states analog input capacitance ? ? 6.0 pf inl integral nonlinearity error ? 1.5 3.0 lsb offset error ? 1.5 3.0 lsb full-scale error ? 1.5 3.0 lsb quantization error ? 0.5 ? lsb absolute accuracy ? 1.5 3.0 lsb dnl differential nonlinearity error ? 0.5 1.0 lsb table 5.21 12-bit a/d conversion characteristics conditions: vcc = pllvcc = avcc = vcc_usb = 2.7 to 3.6v, vrefh = 2.7v to avcc vss = pllvss = avss = vrefl = vss_usb = 0v pclk = 8 to 50mhz t a = -40 to +85 ? c item min. typ. max. unit test conditions resolution 12 12 12 bits conversion time *1 1.0??savcc 3.0 2.0 ? ? s avcc 2.7 analog input capacitance ? ? 30 pf offset error ? 2.0 7.5 lsb full-scale error ? 2.0 7.5 lsb quantization error ? 0.5 ? lsb absolute accuracy ? 2.5 8.0 lsb nonlinearity error ? 2.0 4.0 lsb
r01uh0033jj0110 rev.1.10 page 135 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics 5.6 d/a conversion characteristics 5.7 power-on reset circui t, voltage detection ci rcuit characteristics note 1. the power-off time indicates the time when vcc is below the minimum value of voltage detection levels vpor, vdet1, and vdet2 for the por/ lvd. figure 5.63 power-on reset timing table 5.22 d/a conversion characteristics conditions: vcc = pllvcc = avcc = vcc_usb = 2.7 to 3.6v, vrefh = 2.7v to avcc vss = pllvss = avss = vrefl = vss_usb = 0v t a = -40 to +85 ? c item min. typ. max. unit test conditions resolution 10 10 10 bits conversion time ? ? 3.0 s 20-pf capacitive load absolute accuracy ? 2.0 4.0 lsb 2-m ? resistive load ??3.0lsb4-m ? resistive load ? ? 2.0 lsb 10-m ? resistive load ro output resistance ? 3.6 ? k ? table 5.23 power-on reset circuit, voltage de tection circuit characteristics conditions: vcc = pllvcc = avcc = vcc_usb = 2.7 to 3.6v, vrefh = 2.7v to avcc vss = pllvss = avss = vrefl = vss_usb = 0v t a = -40 to +85 ? c item symbol min. typ. max. unit test conditions voltage detection level power-on reset (por) vpor 2.48 2.58 2.68 v figure 5.63 voltage detection circuit (lvd) vdet1 2.75 2.85 2.95 figure 5.64 and figure 5.65 vdet2 3.05 3.15 3.25 internal reset time tpor 20 35 50 ms min. vcc down time *1 tvoff 200 ? ? s figure 5.64 and figure 5.65 reply delay time tdet ? ? 200 s ,qwhuqdouhvhwvljqdo orzydolg 9&& w 92)) 9 325 w 325 w 325 w ghw
r01uh0033jj0110 rev.1.10 page 136 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics figure 5.64 voltage detection circuit timing (vdet1) figure 5.65 voltage detection circuit timing (vdet2) vcc v det1 t voff t por t det internal reset signal (low valid) vcc v det2 t voff t por t det internal reset signal (low valid)
r01uh0033jj0110 rev.1.10 page 137 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics 5.8 oscillation stop detection timing figure 5.66 oscillation stop detection timing table 5.24 oscillation stop detectio n circuit characteristics conditions: vcc = pllvcc = avcc = vcc_usb = 2.7 to 3.6v, vrefh = 2.7v to avcc vss = pllvss = avss = vrefl = vss_usb = 0v t a = -40 to +85 ? c item symbol min. typ. max. unit test conditions detection time tdr ? ? 1.0 ms figure 5.66 internal oscillation fr equency when oscillation stop is detected f main 0.5 ? 7.0 mhz iclk main clock oscillator internal oscillation nomal operation abnomal operation ostdf* note : * this indicates the ostdf flag in the oscillation detection control register (ostdcr). t dr
r01uh0033jj0110 rev.1.10 page 138 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics 5.9 rom (flash memory for code storage) characteristics note 1. definition of rewrite/erase cycle: the rewrite/erase cycle is the number of erasing for each block. when the rewrite/er ase cycle is n times (n = 1000), erasing ca n be performed n times for each block. for instance, when 256-byte writing is performed 16 times for different addresses in 4- kbyte block and then the entire block is erased, the rewrite/eras e cycle is counted as one. however, writing to the same addres s for several times as one erasing is not enabled (over writing is prohibited). note 2. this indicates the minimum number that guarantees the char acteristics after rewriting. (t he guaranteed value is in the r ange from one to the minimum number.) note 3. this indicates the characteristic when rewrite is performed within the s pecification range including the minimum number. table 5.25 rom (flash memory for code storage) characteristics conditions: vcc = pllvcc = avcc = vcc_usb = 2.7 to 3.6v, vrefh = 2.7v to avcc vss = pllvss = avss = vrefl = vss_usb = 0v temperature range for the programming/erasure operation: t a = -40 to +85 ? c item symbol min. typ. max. unit test conditions programming time 256 bytes t p256 ? 2 12 ms pclk = 50mhz n pec 100 4 kbytes t p4k ?2350ms 16 kbytes t p16k ? 90 200 ms 256 byte t p256 ? 2.4 14.4 ms pclk = 50mhz n pec > 100 4 kbytes t p4k ? 27.6 60 ms 16 kbytes t p16k ? 108 240 ms erasure time 4 kbytes t e4k ? 25 60 ms pclk = 50mhz n pec 100 16 kbytes t e16k ? 100 240 ms 4 kbytes t e4k ? 30 72 ms pclk = 50mhz n pec > 100 16 kbytes t e16k ? 120 288 ms rewrite/erase cycle *1 n pec ??times suspend delay time during writing t spd ? ? 120 s figure 5.67 pclk = 50-mhz operation first suspend delay time during erasing (in suspend priority mode) t sesd1 ? ? 120 s second suspend delay time during erasing (in suspend priority mode) t sesd2 ??1.7ms suspend delay time during erasing (in erasure priority mode) t seed ??1.7ms data hold time *3 t drp 10 ? ? year
r01uh0033jj0110 rev.1.10 page 139 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics 5.10 data flash (flash memory fo r data storage) characteristics note 1. definition of rewrite/erase cycle: the rewrite/erase cycle is the number of er asing for each block. when the rewrite/eras e cycle is n times (n = 30000), erasing c an be performed n times for each block. for instance, when 128-byte writing is performed 16 times for different addresses in 2- kbyte block and then the entire block is erased, the rewrite/eras e cycle is counted as one. however, writing to the same addres s for several times as one erasing is not enabled (over writing is prohibited). note 2. this indicates the minimum number that guarantees the char acteristics after rewriting. (t he guaranteed value is in the r ange from one to the minimum number.) note 3. this indicates the characteristic when rewrite is performed within the s pecification range including the minimum number. table 5.26 data flash (flash memory for data storage) characteristics conditions: vcc = pllvcc = avcc = vcc_usb = 2.7 to 3.6v, vrefh = 2.7v to avcc vss = pllvss = avss = vrefl = vss_usb = 0v temperature range for the programming/erasure operation: t a = -40 to +85 ? c item symbol min. typ. max. unit test conditions programming time 8 bytes t dp8 ? 0.4 2 ms pclk = 50-mhz operation 128 bytes t dp128 ?15ms erasure time 2 kbytes t de2k ? 70 250 ms pclk = 50-mhz operation blank check time 8 bytes t dbc8 ? ? 30 s pclk = 50-mhz operationz 2 kbytes t dbc2k ??0.7ms rewrite/erase cycle *1 n dpec 30000 *2 ??times suspend delay time during writing t dspd ? ? 120 s figure 5.67 pclk = 50-mhz operation first suspend delay time during erasing (in suspend priority mode) t dsesd1 ??120s second suspend delay time during erasing (in suspend priority mode) t dsesd2 ??1.7ms suspend delay time during erasing (in erasure priority mode) t dseed ??1.7ms data hold time *3 t ddrp 10 ? ? year
r01uh0033jj0110 rev.1.10 page 140 of 1931 2010.12.24 RX62N `? rx621 ` 5. electrical characteristics figure 5.67 flash memory write/erase suspend timing fcu command fstatr0.frdy write pulse ? write suspend fcu command fstatr0.frdy erasure pulse ? erasure suspend in suspend priority mode fcu command fstatr0.frdy erasure pulse ? erasure suspend in erasure priority mode program suspend ready not ready ready programming t spd erase suspend ready not ready ready t seed erasing erase suspend resume suspend ready not ready ready not ready t sesd1 t sesd2 erasing erasing
r01ds0052ej0110 rev.1.10 page 141 of 146 feb 10, 2011 RX62N group, rx621 group 5. electrical characteristics figure 5.67 flash memory write/erase suspend timing fcu command fstatr0.frdy write pulse ? write suspend fcu command fstatr0.frdy erasure pulse ? erasure suspend in suspend priority mode fcu command fstatr0.frdy erasure pulse ? erasure suspend in erasure priority mode program suspend ready not ready ready programming t spd erase suspend ready not ready ready t seed erasing erase suspend resume suspend ready not ready ready not ready t sesd1 t sesd2 erasing erasing
r01ds0052ej0110 rev.1.10 page 142 of 146 feb 10, 2011 RX62N group, rx621 group appendix 1. package dimensions appendix 1.pack age dimensions information on the latest version of the package dimensions or mountings has been displayed in "packages" on renesas electronics corp. website. figure a 176-pin lfbga (plbg0176ga-a) package dimensions e a 1 max nom min dimension in millimeters symbol reference a b x y 13.0 0.10 0.80 0.45 0.50 0.55 0.35 0.40 0.45 1.40 13.0 0.08 v w 0.90 0.90 y 1 0.2 0.20 0.15 z e z d s e s d e d 1 e d 1 a x4 a b x m sab s sy s wa s wb v sy 1 23456789101112131415 b c d e f g h j k l m n p r b z e e z a a e d previous code jeita package code renesas code bp-176/bp-176v 0.45g mass[typ.] p-lfbga176-13x13-0.80 plbg0176ga-a
r01ds0052ej0110 rev.1.10 page 143 of 146 feb 10, 2011 RX62N group, rx621 group appendix 1. package dimensions figure b 145-pin tflga (ptlg0145jb-a) package dimensions bas x n b a b ws a ws s ys 1 y s v x4 k j h g f e d c b a 1098765 4 321 d e l 11 12 13 m n z e z e b a e d ptlg0145jb-a p-tflga145-9x9-0.65 0.15g mass[typ.] previous code jeita package code renesas code - e a 1 max nom min dimension in millimeters symbol reference a b x y 9.0 0.1 0.65 0. 30 0. 35 0.40 1.2 9.0 0.08 v w 0.6 0.6 y 1 0.20 0.20 0.15 z e z d s e s d e d
r01ds0052ej0110 rev.1.10 page 144 of 146 feb 10, 2011 RX62N group, rx621 group appendix 1. package dimensions figure c 144-pin lqfp (plqp0144ka-a) package dimensions figure d 100-pin lqfp (plq p0100kb-a) package dimensions terminal cross section b 1 c 1 b p c 1.0 0.125 0.20 1.25 1.25 0.08 0.20 0.145 0.09 0. 270. 220.17 max n ommin dimension in millimeters symbol reference 20. 120. 019.9 d 20. 120. 019.9 e 1.4 a 2 22. 222. 021.8 22. 222. 021.8 1.7 a 0.15 0.1 0.05 0.65 0.5 0.35 l x 8 0 c 0.5 e 0.10 y h d h e a 1 b p b 1 c 1 z d z e l 1 p-lqfp144-20x20-0.50 1.2g mass[typ.] 144p6q-a / fp-144l / fp-144lv plqp0144ka-a renesas code jeita package code previous code f 1 36 37 72 73 108 109 144 *1 *2 *3 x index mark y h e e d h d b p z d z e detail f c a l a 1 a 2 l 1 2. 1. dimensions "*1" and "*2" do not include mold flash. note) dimension "*3" does not include trim offset. e terminal cross section b 1 c 1 b p c 2. 1. dimensions "*1" and "*2" do not include mold flash. note) dimension "*3" does not include trim offset. y index mark x 12 5 26 50 51 75 76 100 f *1 *3 *2 z e z d e d h d h e b p detail f l 1 a 2 a 1 l a c l 1 z e z d c 1 b 1 b p a 1 h e h d y 0.08 e 0.5 c 0 8 x l 0.35 0.5 0.65 0.05 0.1 0.15 a 1.7 15.81 6 . 01 6 . 2 15 . 816 . 016 .2 a 2 1.4 e 13.91 4.01 4.1 d 13.91 4.01 4.1 reference symbol dimension in millimeters min n om max 0. 15 0. 20 0.25 0.09 0.145 0.20 0.08 1.0 1.0 0.18 0.125 1.0 previous code jeita package code renesas code plqp0100kb- a 100p6q-a / fp-100u / fp-100uv mass[typ.] 0.6g p-lqfp100-14x14-0.50 e
r01ds0052ej0110 rev.1.10 page 145 of 146 feb 10, 2011 RX62N group, rx621 group appendix 1. package dimensions figure e 85-pin tflga (ptlg0085ja-a) package dimensions b a b ws a ws s ys 1 ys v 1234 5678910 a b c d e f g h j k a ptlg0085ja-a p-tflga85-7x7-0.65 d e d e s d s e z d z e z d z e mass[typ.] 0.1g tlp-85v renesas code jeita package code previous code 0.15 0.20 0.2 y 1 0.575 0.575 w v 0.08 7.0 1.20 0.40 0.35 0.30 0.65 0.10 7.0 y x b a reference symbol dimension in millimeters min n om max a 1 e e e bas b m 4
r01ds0052ej0110 rev.1.10 page 146 of 146 feb 10, 2011 RX62N group, rx621 group revision history revision history RX62N group, rx621 group datasheet rev. date description page summary 1.00 2011.02.04 ? first edition issued 1.10 2011.02.10 ? features reviewed all trademarks and registered trademarks are the property of thei r respective owners. revision history

▲Up To Search▲

Price & Availability of RX62N

	To Download RX62N Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .